* [Intel-gfx] [PATCH 1/4] drm/i915: split out PCI config space registers from i915_reg.h
@ 2022-01-10 9:57 Jani Nikula
2022-01-10 9:57 ` [Intel-gfx] [PATCH 2/4] drm/i915: split out vlv sideband " Jani Nikula
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Jani Nikula @ 2022-01-10 9:57 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The PCI config space registers don't really belong next to the MMIO
register definitions.
v2: Fix copyright year (Matt)
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_backlight.c | 1 +
drivers/gpu/drm/i915/display/intel_cdclk.c | 1 +
drivers/gpu/drm/i915/display/intel_opregion.c | 1 +
drivers/gpu/drm/i915/display/intel_overlay.c | 1 +
drivers/gpu/drm/i915/gt/intel_reset.c | 1 +
drivers/gpu/drm/i915/i915_driver.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 78 -----------------
drivers/gpu/drm/i915/i915_suspend.c | 1 +
drivers/gpu/drm/i915/intel_pci_config.h | 85 +++++++++++++++++++
9 files changed, 92 insertions(+), 78 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_pci_config.h
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 2db3b792aca6..98f7ea44042f 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -13,6 +13,7 @@
#include "intel_dp_aux_backlight.h"
#include "intel_dsi_dcs_backlight.h"
#include "intel_panel.h"
+#include "intel_pci_config.h"
/**
* scale - scale values from one range to another
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 249f81a80eb7..1f13398e8ac2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -31,6 +31,7 @@
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_pci_config.h"
#include "intel_pcode.h"
#include "intel_psr.h"
#include "vlv_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 985790a66a4d..af9d30f56cc1 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -35,6 +35,7 @@
#include "intel_backlight.h"
#include "intel_display_types.h"
#include "intel_opregion.h"
+#include "intel_pci_config.h"
#define OPREGION_HEADER_OFFSET 0
#define OPREGION_ACPI_OFFSET 0x100
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 1a376e9a1ff3..991624a1351a 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -38,6 +38,7 @@
#include "intel_display_types.h"
#include "intel_frontbuffer.h"
#include "intel_overlay.h"
+#include "intel_pci_config.h"
/* Limits for overlay size. According to intel doc, the real limits are:
* Y width: 4095, UV width (planar): 2047, Y height: 2047,
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 7be0002d9d70..a75ef7bf36c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -19,6 +19,7 @@
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
+#include "intel_pci_config.h"
#include "intel_reset.h"
#include "uc/intel_guc.h"
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 5f2343389b5e..762bf7e65784 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -86,6 +86,7 @@
#include "intel_dram.h"
#include "intel_gvt.h"
#include "intel_memory_region.h"
+#include "intel_pci_config.h"
#include "intel_pcode.h"
#include "intel_pm.h"
#include "intel_region_ttm.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e20e832162b4..baa0b9e6acb2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -275,84 +275,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
-/* PCI config space */
-
-#define MCHBAR_I915 0x44
-#define MCHBAR_I965 0x48
-#define MCHBAR_SIZE (4 * 4096)
-
-#define DEVEN 0x54
-#define DEVEN_MCHBAR_EN (1 << 28)
-
-/* BSM in include/drm/i915_drm.h */
-
-#define HPLLCC 0xc0 /* 85x only */
-#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
-#define GC_CLOCK_133_200 (0 << 0)
-#define GC_CLOCK_100_200 (1 << 0)
-#define GC_CLOCK_100_133 (2 << 0)
-#define GC_CLOCK_133_266 (3 << 0)
-#define GC_CLOCK_133_200_2 (4 << 0)
-#define GC_CLOCK_133_266_2 (5 << 0)
-#define GC_CLOCK_166_266 (6 << 0)
-#define GC_CLOCK_166_250 (7 << 0)
-
-#define I915_GDRST 0xc0 /* PCI config register */
-#define GRDOM_FULL (0 << 2)
-#define GRDOM_RENDER (1 << 2)
-#define GRDOM_MEDIA (3 << 2)
-#define GRDOM_MASK (3 << 2)
-#define GRDOM_RESET_STATUS (1 << 1)
-#define GRDOM_RESET_ENABLE (1 << 0)
-
-/* BSpec only has register offset, PCI device and bit found empirically */
-#define I830_CLOCK_GATE 0xc8 /* device 0 */
-#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
-
-#define GCDGMBUS 0xcc
-
-#define GCFGC2 0xda
-#define GCFGC 0xf0 /* 915+ only */
-#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
-#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
-#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
-#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
-#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
-#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
-#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
-#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
-#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
-#define GC_DISPLAY_CLOCK_MASK (7 << 4)
-#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
-#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
-#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
-#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
-#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
-#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
-#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
-#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
-#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
-#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
-#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
-#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
-#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
-#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
-#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
-#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
-#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
-#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
-#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
-
-#define ASLE 0xe4
-#define ASLS 0xfc
-
-#define SWSCI 0xe8
-#define SWSCI_SCISEL (1 << 15)
-#define SWSCI_GSSCIE (1 << 0)
-
-#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
-
-
#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
#define ILK_GRDOM_FULL (0 << 1)
#define ILK_GRDOM_RENDER (1 << 1)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index f7b55f34dba8..889f5b7dc78e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -32,6 +32,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_suspend.h"
+#include "intel_pci_config.h"
static void intel_save_swf(struct drm_i915_private *dev_priv)
{
diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/drivers/gpu/drm/i915/intel_pci_config.h
new file mode 100644
index 000000000000..12cd9d4f23de
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_pci_config.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_PCI_CONFIG_H__
+#define __INTEL_PCI_CONFIG_H__
+
+/* BSM in include/drm/i915_drm.h */
+
+#define MCHBAR_I915 0x44
+#define MCHBAR_I965 0x48
+#define MCHBAR_SIZE (4 * 4096)
+
+#define DEVEN 0x54
+#define DEVEN_MCHBAR_EN (1 << 28)
+
+#define HPLLCC 0xc0 /* 85x only */
+#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
+#define GC_CLOCK_133_200 (0 << 0)
+#define GC_CLOCK_100_200 (1 << 0)
+#define GC_CLOCK_100_133 (2 << 0)
+#define GC_CLOCK_133_266 (3 << 0)
+#define GC_CLOCK_133_200_2 (4 << 0)
+#define GC_CLOCK_133_266_2 (5 << 0)
+#define GC_CLOCK_166_266 (6 << 0)
+#define GC_CLOCK_166_250 (7 << 0)
+
+#define I915_GDRST 0xc0
+#define GRDOM_FULL (0 << 2)
+#define GRDOM_RENDER (1 << 2)
+#define GRDOM_MEDIA (3 << 2)
+#define GRDOM_MASK (3 << 2)
+#define GRDOM_RESET_STATUS (1 << 1)
+#define GRDOM_RESET_ENABLE (1 << 0)
+
+/* BSpec only has register offset, PCI device and bit found empirically */
+#define I830_CLOCK_GATE 0xc8 /* device 0 */
+#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
+
+#define GCDGMBUS 0xcc
+
+#define GCFGC2 0xda
+#define GCFGC 0xf0 /* 915+ only */
+#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
+#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
+#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
+#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
+#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
+#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
+#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
+#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
+#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
+#define GC_DISPLAY_CLOCK_MASK (7 << 4)
+#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
+#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
+#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
+#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
+#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
+#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
+#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
+#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
+#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
+#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
+#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
+#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
+#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
+#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
+#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
+#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
+#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
+#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
+#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
+
+#define ASLE 0xe4
+#define ASLS 0xfc
+
+#define SWSCI 0xe8
+#define SWSCI_SCISEL (1 << 15)
+#define SWSCI_GSSCIE (1 << 0)
+
+/* legacy/combination backlight modes, also called LBB */
+#define LBPC 0xf4
+
+#endif /* __INTEL_PCI_CONFIG_H__ */
--
2.30.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915: split out vlv sideband registers from i915_reg.h
2022-01-10 9:57 [Intel-gfx] [PATCH 1/4] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
@ 2022-01-10 9:57 ` Jani Nikula
2022-01-10 14:32 ` Jani Nikula
2022-01-10 9:57 ` [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h Jani Nikula
` (5 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2022-01-10 9:57 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add a dedicated file vlv_sideband_reg.h for the VLV/CHV sideband
registers. The sideband registers macros are needed by the same files
that need vlv_sideband.h, so include the definitions from there.
v2: Fix copyright year (Matt)
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 171 ----------------------
drivers/gpu/drm/i915/vlv_sideband.h | 2 +
drivers/gpu/drm/i915/vlv_sideband_reg.h | 180 ++++++++++++++++++++++++
3 files changed, 182 insertions(+), 171 deletions(-)
create mode 100644 drivers/gpu/drm/i915/vlv_sideband_reg.h
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index baa0b9e6acb2..61ade07068c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1166,177 +1166,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
-/* See configdb bunit SB addr map */
-#define BUNIT_REG_BISOC 0x11
-
-/* PUNIT_REG_*SSPM0 */
-#define _SSPM0_SSC(val) ((val) << 0)
-#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
-#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
-#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
-#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
-#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
-#define _SSPM0_SSS(val) ((val) << 24)
-#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
-#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
-#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
-#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
-#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
-
-/* PUNIT_REG_*SSPM1 */
-#define SSPM1_FREQSTAT_SHIFT 24
-#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
-#define SSPM1_FREQGUAR_SHIFT 8
-#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
-#define SSPM1_FREQ_SHIFT 0
-#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
-
-#define PUNIT_REG_VEDSSPM0 0x32
-#define PUNIT_REG_VEDSSPM1 0x33
-
-#define PUNIT_REG_DSPSSPM 0x36
-#define DSPFREQSTAT_SHIFT_CHV 24
-#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
-#define DSPFREQGUAR_SHIFT_CHV 8
-#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
-#define DSPFREQSTAT_SHIFT 30
-#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
-#define DSPFREQGUAR_SHIFT 14
-#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
-#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
-#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
-#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
-#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
-#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
-#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
-#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
-#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
-#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
-#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
-#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
-#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
-#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
-#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
-#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
-
-#define PUNIT_REG_ISPSSPM0 0x39
-#define PUNIT_REG_ISPSSPM1 0x3a
-
-#define PUNIT_REG_PWRGT_CTRL 0x60
-#define PUNIT_REG_PWRGT_STATUS 0x61
-#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
-#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
-#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
-#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
-#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
-
-#define PUNIT_PWGT_IDX_RENDER 0
-#define PUNIT_PWGT_IDX_MEDIA 1
-#define PUNIT_PWGT_IDX_DISP2D 3
-#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
-#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
-#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
-#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
-#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
-#define PUNIT_PWGT_IDX_DPIO_RX0 10
-#define PUNIT_PWGT_IDX_DPIO_RX1 11
-#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
-
-#define PUNIT_REG_GPU_LFM 0xd3
-#define PUNIT_REG_GPU_FREQ_REQ 0xd4
-#define PUNIT_REG_GPU_FREQ_STS 0xd8
-#define GPLLENABLE (1 << 4)
-#define GENFREQSTATUS (1 << 0)
-#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
-#define PUNIT_REG_CZ_TIMESTAMP 0xce
-
-#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
-#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
-
-#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
-#define FB_GFX_FREQ_FUSE_MASK 0xff
-#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
-#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
-#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
-
-#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
-#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
-
-#define PUNIT_REG_DDR_SETUP2 0x139
-#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
-#define FORCE_DDR_LOW_FREQ (1 << 1)
-#define FORCE_DDR_HIGH_FREQ (1 << 0)
-
-#define PUNIT_GPU_STATUS_REG 0xdb
-#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
-#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
-#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
-#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
-
-#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
-#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
-#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
-
-#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
-#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
-#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
-#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
-#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
-#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
-#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
-#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
-#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
-#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
-
-#define VLV_TURBO_SOC_OVERRIDE 0x04
-#define VLV_OVERRIDE_EN 1
-#define VLV_SOC_TDP_EN (1 << 1)
-#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
-#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
-
-/* vlv2 north clock has */
-#define CCK_FUSE_REG 0x8
-#define CCK_FUSE_HPLL_FREQ_MASK 0x3
-#define CCK_REG_DSI_PLL_FUSE 0x44
-#define CCK_REG_DSI_PLL_CONTROL 0x48
-#define DSI_PLL_VCO_EN (1 << 31)
-#define DSI_PLL_LDO_GATE (1 << 30)
-#define DSI_PLL_P1_POST_DIV_SHIFT 17
-#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
-#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
-#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
-#define DSI_PLL_MUX_MASK (3 << 9)
-#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
-#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
-#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
-#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
-#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
-#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
-#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
-#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
-#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
-#define DSI_PLL_LOCK (1 << 0)
-#define CCK_REG_DSI_PLL_DIVIDER 0x4c
-#define DSI_PLL_LFSR (1 << 31)
-#define DSI_PLL_FRACTION_EN (1 << 30)
-#define DSI_PLL_FRAC_COUNTER_SHIFT 27
-#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
-#define DSI_PLL_USYNC_CNT_SHIFT 18
-#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
-#define DSI_PLL_N1_DIV_SHIFT 16
-#define DSI_PLL_N1_DIV_MASK (3 << 16)
-#define DSI_PLL_M1_DIV_SHIFT 0
-#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
-#define CCK_CZ_CLOCK_CONTROL 0x62
-#define CCK_GPLL_CLOCK_CONTROL 0x67
-#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
-#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
-#define CCK_TRUNK_FORCE_ON (1 << 17)
-#define CCK_TRUNK_FORCE_OFF (1 << 16)
-#define CCK_FREQUENCY_STATUS (0x1f << 8)
-#define CCK_FREQUENCY_STATUS_SHIFT 8
-#define CCK_FREQUENCY_VALUES (0x1f << 0)
-
/* DPIO registers */
#define DPIO_DEVFN 0
diff --git a/drivers/gpu/drm/i915/vlv_sideband.h b/drivers/gpu/drm/i915/vlv_sideband.h
index d7732f612e7f..9ce283d96b80 100644
--- a/drivers/gpu/drm/i915/vlv_sideband.h
+++ b/drivers/gpu/drm/i915/vlv_sideband.h
@@ -9,6 +9,8 @@
#include <linux/bitops.h>
#include <linux/types.h>
+#include "vlv_sideband_reg.h"
+
enum pipe;
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/vlv_sideband_reg.h b/drivers/gpu/drm/i915/vlv_sideband_reg.h
new file mode 100644
index 000000000000..b7fbff3d0409
--- /dev/null
+++ b/drivers/gpu/drm/i915/vlv_sideband_reg.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _VLV_SIDEBAND_REG_H_
+#define _VLV_SIDEBAND_REG_H_
+
+/* See configdb bunit SB addr map */
+#define BUNIT_REG_BISOC 0x11
+
+/* PUNIT_REG_*SSPM0 */
+#define _SSPM0_SSC(val) ((val) << 0)
+#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
+#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
+#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
+#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
+#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
+#define _SSPM0_SSS(val) ((val) << 24)
+#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
+#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
+#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
+#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
+#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
+
+/* PUNIT_REG_*SSPM1 */
+#define SSPM1_FREQSTAT_SHIFT 24
+#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
+#define SSPM1_FREQGUAR_SHIFT 8
+#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
+#define SSPM1_FREQ_SHIFT 0
+#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
+
+#define PUNIT_REG_VEDSSPM0 0x32
+#define PUNIT_REG_VEDSSPM1 0x33
+
+#define PUNIT_REG_DSPSSPM 0x36
+#define DSPFREQSTAT_SHIFT_CHV 24
+#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
+#define DSPFREQGUAR_SHIFT_CHV 8
+#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
+#define DSPFREQSTAT_SHIFT 30
+#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
+#define DSPFREQGUAR_SHIFT 14
+#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
+#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
+#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
+#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
+#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
+#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
+#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
+#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
+#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
+#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
+#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
+#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
+#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
+#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
+#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
+#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
+
+#define PUNIT_REG_ISPSSPM0 0x39
+#define PUNIT_REG_ISPSSPM1 0x3a
+
+#define PUNIT_REG_PWRGT_CTRL 0x60
+#define PUNIT_REG_PWRGT_STATUS 0x61
+#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
+
+#define PUNIT_PWGT_IDX_RENDER 0
+#define PUNIT_PWGT_IDX_MEDIA 1
+#define PUNIT_PWGT_IDX_DISP2D 3
+#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
+#define PUNIT_PWGT_IDX_DPIO_RX0 10
+#define PUNIT_PWGT_IDX_DPIO_RX1 11
+#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
+
+#define PUNIT_REG_GPU_LFM 0xd3
+#define PUNIT_REG_GPU_FREQ_REQ 0xd4
+#define PUNIT_REG_GPU_FREQ_STS 0xd8
+#define GPLLENABLE (1 << 4)
+#define GENFREQSTATUS (1 << 0)
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
+#define PUNIT_REG_CZ_TIMESTAMP 0xce
+
+#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+
+#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
+#define FB_GFX_FREQ_FUSE_MASK 0xff
+#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
+#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
+#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
+
+#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
+#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
+
+#define PUNIT_REG_DDR_SETUP2 0x139
+#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
+#define FORCE_DDR_LOW_FREQ (1 << 1)
+#define FORCE_DDR_HIGH_FREQ (1 << 0)
+
+#define PUNIT_GPU_STATUS_REG 0xdb
+#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
+#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
+#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
+#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
+
+#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
+
+#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
+#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
+#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
+#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
+#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
+#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
+#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
+#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
+#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
+#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
+
+#define VLV_TURBO_SOC_OVERRIDE 0x04
+#define VLV_OVERRIDE_EN 1
+#define VLV_SOC_TDP_EN (1 << 1)
+#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
+#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
+
+/* vlv2 north clock has */
+#define CCK_FUSE_REG 0x8
+#define CCK_FUSE_HPLL_FREQ_MASK 0x3
+#define CCK_REG_DSI_PLL_FUSE 0x44
+#define CCK_REG_DSI_PLL_CONTROL 0x48
+#define DSI_PLL_VCO_EN (1 << 31)
+#define DSI_PLL_LDO_GATE (1 << 30)
+#define DSI_PLL_P1_POST_DIV_SHIFT 17
+#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
+#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
+#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
+#define DSI_PLL_MUX_MASK (3 << 9)
+#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
+#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
+#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
+#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
+#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
+#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
+#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
+#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
+#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
+#define DSI_PLL_LOCK (1 << 0)
+#define CCK_REG_DSI_PLL_DIVIDER 0x4c
+#define DSI_PLL_LFSR (1 << 31)
+#define DSI_PLL_FRACTION_EN (1 << 30)
+#define DSI_PLL_FRAC_COUNTER_SHIFT 27
+#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
+#define DSI_PLL_USYNC_CNT_SHIFT 18
+#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
+#define DSI_PLL_N1_DIV_SHIFT 16
+#define DSI_PLL_N1_DIV_MASK (3 << 16)
+#define DSI_PLL_M1_DIV_SHIFT 0
+#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
+#define CCK_CZ_CLOCK_CONTROL 0x62
+#define CCK_GPLL_CLOCK_CONTROL 0x67
+#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
+#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
+#define CCK_TRUNK_FORCE_ON (1 << 17)
+#define CCK_TRUNK_FORCE_OFF (1 << 16)
+#define CCK_FREQUENCY_STATUS (0x1f << 8)
+#define CCK_FREQUENCY_STATUS_SHIFT 8
+#define CCK_FREQUENCY_VALUES (0x1f << 0)
+
+#endif /* _VLV_SIDEBAND_REG_H_ */
--
2.30.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-01-10 9:57 [Intel-gfx] [PATCH 1/4] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
2022-01-10 9:57 ` [Intel-gfx] [PATCH 2/4] drm/i915: split out vlv sideband " Jani Nikula
@ 2022-01-10 9:57 ` Jani Nikula
2022-01-10 16:03 ` Ville Syrjälä
2022-01-10 9:57 ` [Intel-gfx] [PATCH 4/4] drm/i915: remove VGA register definitions Jani Nikula
` (4 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2022-01-10 9:57 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The video/vga.h has macros for the VGA registers. Switch to use them.
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_vga.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
index fa779f7ea415..43c12036c1fa 100644
--- a/drivers/gpu/drm/i915/display/intel_vga.c
+++ b/drivers/gpu/drm/i915/display/intel_vga.c
@@ -7,6 +7,7 @@
#include <linux/vgaarb.h>
#include <drm/i915_drm.h>
+#include <video/vga.h>
#include "i915_drv.h"
#include "intel_de.h"
@@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
- outb(SR01, VGA_SR_INDEX);
- sr1 = inb(VGA_SR_DATA);
- outb(sr1 | 1 << 5, VGA_SR_DATA);
+ outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I);
+ sr1 = inb(VGA_SEQ_D);
+ outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D);
vga_put(pdev, VGA_RSRC_LEGACY_IO);
udelay(300);
@@ -92,7 +93,7 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915)
* and error messages.
*/
vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
- outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
+ outb(inb(VGA_MIS_R), VGA_MIS_W);
vga_put(pdev, VGA_RSRC_LEGACY_IO);
}
--
2.30.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: remove VGA register definitions
2022-01-10 9:57 [Intel-gfx] [PATCH 1/4] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
2022-01-10 9:57 ` [Intel-gfx] [PATCH 2/4] drm/i915: split out vlv sideband " Jani Nikula
2022-01-10 9:57 ` [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h Jani Nikula
@ 2022-01-10 9:57 ` Jani Nikula
2022-01-10 10:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h Patchwork
` (3 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-01-10 9:57 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The only user of the VGA registers has switched to using the definitions
in linux/vga.h, so these have become redundant. Remove them.
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 41 ---------------------------------
1 file changed, 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 61ade07068c8..459105f232d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -460,48 +460,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
-/* VGA stuff */
-
-#define VGA_ST01_MDA 0x3ba
-#define VGA_ST01_CGA 0x3da
-
#define _VGA_MSR_WRITE _MMIO(0x3c2)
-#define VGA_MSR_WRITE 0x3c2
-#define VGA_MSR_READ 0x3cc
-#define VGA_MSR_MEM_EN (1 << 1)
-#define VGA_MSR_CGA_MODE (1 << 0)
-
-#define VGA_SR_INDEX 0x3c4
-#define SR01 1
-#define VGA_SR_DATA 0x3c5
-
-#define VGA_AR_INDEX 0x3c0
-#define VGA_AR_VID_EN (1 << 5)
-#define VGA_AR_DATA_WRITE 0x3c0
-#define VGA_AR_DATA_READ 0x3c1
-
-#define VGA_GR_INDEX 0x3ce
-#define VGA_GR_DATA 0x3cf
-/* GR05 */
-#define VGA_GR_MEM_READ_MODE_SHIFT 3
-#define VGA_GR_MEM_READ_MODE_PLANE 1
-/* GR06 */
-#define VGA_GR_MEM_MODE_MASK 0xc
-#define VGA_GR_MEM_MODE_SHIFT 2
-#define VGA_GR_MEM_A0000_AFFFF 0
-#define VGA_GR_MEM_A0000_BFFFF 1
-#define VGA_GR_MEM_B0000_B7FFF 2
-#define VGA_GR_MEM_B0000_BFFFF 3
-
-#define VGA_DACMASK 0x3c6
-#define VGA_DACRX 0x3c7
-#define VGA_DACWX 0x3c8
-#define VGA_DACDATA 0x3c9
-
-#define VGA_CR_INDEX_MDA 0x3b4
-#define VGA_CR_DATA_MDA 0x3b5
-#define VGA_CR_INDEX_CGA 0x3d4
-#define VGA_CR_DATA_CGA 0x3d5
#define MI_PREDICATE_SRC0 _MMIO(0x2400)
#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
--
2.30.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h
2022-01-10 9:57 [Intel-gfx] [PATCH 1/4] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
` (2 preceding siblings ...)
2022-01-10 9:57 ` [Intel-gfx] [PATCH 4/4] drm/i915: remove VGA register definitions Jani Nikula
@ 2022-01-10 10:30 ` Patchwork
2022-01-10 10:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-01-10 10:30 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h
URL : https://patchwork.freedesktop.org/series/98672/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6a1b0048ac62 drm/i915: split out PCI config space registers from i915_reg.h
-:190: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#190:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 218 lines checked
92dafa7e60d7 drm/i915: split out vlv sideband registers from i915_reg.h
-:212: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#212:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 365 lines checked
1eaf1d9cc0f5 drm/i915/vga: switch to use VGA definitions from video/vga.h
26f16fbaa294 drm/i915: remove VGA register definitions
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h
2022-01-10 9:57 [Intel-gfx] [PATCH 1/4] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
` (3 preceding siblings ...)
2022-01-10 10:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h Patchwork
@ 2022-01-10 10:31 ` Patchwork
2022-01-10 11:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-10 13:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-01-10 10:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h
URL : https://patchwork.freedesktop.org/series/98672/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h
2022-01-10 9:57 [Intel-gfx] [PATCH 1/4] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
` (4 preceding siblings ...)
2022-01-10 10:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-01-10 11:03 ` Patchwork
2022-01-10 13:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-01-10 11:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5539 bytes --]
== Series Details ==
Series: series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h
URL : https://patchwork.freedesktop.org/series/98672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11058 -> Patchwork_21947
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/index.html
Participating hosts (41 -> 34)
------------------------------
Additional (1): fi-kbl-soraka
Missing (8): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21947 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770: NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-hsw-4770/igt@amdgpu/amd_basic@cs-gfx.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +22 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-tgl-1115g4: [PASS][3] -> [FAIL][4] ([i915#1888])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#1886] / [i915#2291])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][8] -> [INCOMPLETE][9] ([i915#3921])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#4269])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][14] ([i915#4785]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11058 -> Patchwork_21947
CI-20190529: 20190529
CI_DRM_11058: fbce7b8d8df5af8d404b6aeaf63779f91bdbeb5d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6325: ac29e097d4ff0f2e269a955ca86c5eb23908467a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21947: 26f16fbaa294e0f56afb00d65284370eefcd45f1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
26f16fbaa294 drm/i915: remove VGA register definitions
1eaf1d9cc0f5 drm/i915/vga: switch to use VGA definitions from video/vga.h
92dafa7e60d7 drm/i915: split out vlv sideband registers from i915_reg.h
6a1b0048ac62 drm/i915: split out PCI config space registers from i915_reg.h
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/index.html
[-- Attachment #2: Type: text/html, Size: 6748 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h
2022-01-10 9:57 [Intel-gfx] [PATCH 1/4] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
` (5 preceding siblings ...)
2022-01-10 11:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-01-10 13:20 ` Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-01-10 13:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30312 bytes --]
== Series Details ==
Series: series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h
URL : https://patchwork.freedesktop.org/series/98672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11058_full -> Patchwork_21947_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21947_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_flush@basic-wb-prw-default:
- {shard-rkl}: NOTRUN -> [INCOMPLETE][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-rkl-5/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_exec_whisper@basic-fds-all:
- {shard-rkl}: NOTRUN -> ([PASS][2], [FAIL][3])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-rkl-4/igt@gem_exec_whisper@basic-fds-all.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-rkl-5/igt@gem_exec_whisper@basic-fds-all.html
* igt@gem_mmap_gtt@flink-race:
- {shard-rkl}: [PASS][4] -> ([PASS][5], [INCOMPLETE][6]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-rkl-1/igt@gem_mmap_gtt@flink-race.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-rkl-4/igt@gem_mmap_gtt@flink-race.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-rkl-5/igt@gem_mmap_gtt@flink-race.html
* igt@gem_userptr_blits@create-destroy-sync:
- {shard-rkl}: [PASS][7] -> [INCOMPLETE][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-rkl-4/igt@gem_userptr_blits@create-destroy-sync.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-rkl-5/igt@gem_userptr_blits@create-destroy-sync.html
Known issues
------------
Here are the changes found in Patchwork_21947_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [FAIL][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33]) ([i915#4392]) -> ([PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk3/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk4/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk4/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk4/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk8/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk8/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk8/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk9/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk9/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk9/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk9/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk2/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk2/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk2/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk3/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk3/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk6/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk5/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk5/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk4/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk3/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk3/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk2/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk2/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk2/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk1/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk1/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk1/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk9/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk9/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk8/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk8/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk8/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk7/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk7/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk7/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk6/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk6/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-glk: NOTRUN -> [DMESG-WARN][59] ([i915#3002])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk1/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][60] -> [DMESG-WARN][61] ([i915#180]) +4 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][62] -> [FAIL][63] ([i915#2410])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][64] -> [SKIP][65] ([i915#4525])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-iclb6/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][66] ([i915#4547])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][67] -> [FAIL][68] ([i915#2842])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [PASS][69] -> [FAIL][70] ([i915#2842])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][71] -> [FAIL][72] ([i915#2842])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][73] -> [FAIL][74] ([i915#2842]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_whisper@basic-queues-priority-all:
- shard-iclb: [PASS][75] -> [INCOMPLETE][76] ([i915#1895])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-iclb5/igt@gem_exec_whisper@basic-queues-priority-all.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-iclb1/igt@gem_exec_whisper@basic-queues-priority-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][77] -> [SKIP][78] ([i915#2190])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-tglb3/igt@gem_huc_copy@huc-copy.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb6/igt@gem_huc_copy@huc-copy.html
- shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2190])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl4/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#4613])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl1/igt@gem_lmem_swapping@parallel-random-engines.html
- shard-tglb: NOTRUN -> [SKIP][81] ([i915#4613])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb1/igt@gem_lmem_swapping@parallel-random-engines.html
- shard-skl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#4613]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@smem-oom:
- shard-kbl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#4613]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl6/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#3323])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@gem_userptr_blits@dmabuf-sync.html
- shard-glk: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#3323])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk1/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][86] ([i915#3002]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl4/igt@gem_userptr_blits@input-checking.html
* igt@gen9_exec_parse@unaligned-access:
- shard-iclb: NOTRUN -> [SKIP][87] ([i915#2856])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-iclb8/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][88] -> [INCOMPLETE][89] ([i915#3921])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-snb4/igt@i915_selftest@live@hangcheck.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [PASS][90] -> [DMESG-WARN][91] ([i915#118])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk7/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][92] ([i915#3743])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-glk: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#3777])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][94] ([i915#3763])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#3777]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#3886]) +3 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl1/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
- shard-tglb: NOTRUN -> [SKIP][97] ([i915#3689] / [i915#3886])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb1/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#3886]) +10 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl3/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#3886]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl4/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#3886]) +3 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk1/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-cmp-planar-formats:
- shard-glk: NOTRUN -> [SKIP][101] ([fdo#109271] / [fdo#111827]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk7/igt@kms_chamelium@hdmi-cmp-planar-formats.html
* igt@kms_chamelium@vga-hpd-fast:
- shard-skl: NOTRUN -> [SKIP][102] ([fdo#109271] / [fdo#111827]) +9 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl3/igt@kms_chamelium@vga-hpd-fast.html
* igt@kms_color@pipe-d-invalid-ctm-matrix-sizes:
- shard-glk: NOTRUN -> [SKIP][103] ([fdo#109271]) +50 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk7/igt@kms_color@pipe-d-invalid-ctm-matrix-sizes.html
* igt@kms_color_chamelium@pipe-b-ctm-blue-to-red:
- shard-apl: NOTRUN -> [SKIP][104] ([fdo#109271] / [fdo#111827]) +3 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl1/igt@kms_color_chamelium@pipe-b-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-negative:
- shard-tglb: NOTRUN -> [SKIP][105] ([fdo#109284] / [fdo#111827]) +2 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-negative.html
* igt@kms_color_chamelium@pipe-c-gamma:
- shard-kbl: NOTRUN -> [SKIP][106] ([fdo#109271] / [fdo#111827]) +10 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl6/igt@kms_color_chamelium@pipe-c-gamma.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][107] ([i915#1319])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl1/igt@kms_content_protection@lic.html
- shard-tglb: NOTRUN -> [SKIP][108] ([i915#1063])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb1/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [PASS][109] -> [INCOMPLETE][110] ([i915#2828] / [i915#300])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][111] -> [FAIL][112] ([i915#72])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109274] / [fdo#109278])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-iclb8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][114] -> [FAIL][115] ([i915#79])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][116] -> [FAIL][117] ([i915#79]) +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][118] -> [DMESG-WARN][119] ([i915#180]) +4 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: [PASS][120] -> [INCOMPLETE][121] ([i915#4839])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-skl7/igt@kms_flip@flip-vs-suspend@b-edp1.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][122] -> [INCOMPLETE][123] ([i915#180] / [i915#636]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][124] ([fdo#109271]) +117 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][125] ([fdo#109271]) +182 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff:
- shard-tglb: NOTRUN -> [SKIP][126] ([fdo#109280] / [fdo#111825]) +3 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][127] -> [FAIL][128] ([i915#1188]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: NOTRUN -> [FAIL][129] ([i915#1188])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#533]) +2 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl1/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
- shard-skl: NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#533])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][132] ([fdo#109271] / [i915#533]) +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][133] ([i915#265]) +1 similar issue
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][134] ([fdo#108145] / [i915#265])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][135] ([i915#265])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][136] ([i915#265])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_cursor@pipe-c-overlay-size-256:
- shard-glk: [PASS][137] -> [FAIL][138] ([i915#1888] / [i915#4729])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-glk5/igt@kms_plane_cursor@pipe-c-overlay-size-256.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-glk7/igt@kms_plane_cursor@pipe-c-overlay-size-256.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#658]) +1 similar issue
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
- shard-tglb: NOTRUN -> [SKIP][140] ([i915#2920])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][141] ([fdo#109271] / [i915#658]) +2 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-kbl: NOTRUN -> [SKIP][142] ([fdo#109271] / [i915#658]) +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl3/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: NOTRUN -> [SKIP][143] ([fdo#109441])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][144] -> [SKIP][145] ([fdo#109441])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-iclb3/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][146] ([fdo#109271]) +61 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl1/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@kms_writeback@writeback-fb-id:
- shard-skl: NOTRUN -> [SKIP][147] ([fdo#109271] / [i915#2437])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-c-source-outp-complete:
- shard-tglb: NOTRUN -> [SKIP][148] ([i915#2530])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb1/igt@nouveau_crc@pipe-c-source-outp-complete.html
* igt@perf@short-reads:
- shard-skl: NOTRUN -> [FAIL][149] ([i915#51])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@perf@short-reads.html
* igt@runner@aborted:
- shard-skl: NOTRUN -> ([FAIL][150], [FAIL][151], [FAIL][152]) ([i915#3002] / [i915#4312])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl4/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl9/igt@runner@aborted.html
* igt@sysfs_clients@create:
- shard-skl: NOTRUN -> [SKIP][153] ([fdo#109271] / [i915#2994])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl3/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-3:
- shard-kbl: NOTRUN -> [SKIP][154] ([fdo#109271] / [i915#2994])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-kbl4/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@sema-25:
- shard-apl: NOTRUN -> [SKIP][155] ([fdo#109271] / [i915#2994])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-apl8/igt@sysfs_clients@sema-25.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-skl: [INCOMPLETE][156] ([i915#4793]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-skl8/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-skl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@many-contexts:
- {shard-rkl}: [FAIL][158] ([i915#2410]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-rkl-6/igt@gem_ctx_persistence@many-contexts.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-rkl-6/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_ctx_persistence@smoketest:
- {shard-dg1}: [DMESG-WARN][160] ([i915#4892]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-dg1-19/igt@gem_ctx_persistence@smoketest.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-dg1-18/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@in-flight-contexts-10ms:
- {shard-tglu}: [TIMEOUT][162] ([i915#3063]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-tglu-2/igt@gem_eio@in-flight-contexts-10ms.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglu-2/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [TIMEOUT][164] ([i915#3063]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11058/shard-tglb3/igt@gem_eio@in-flight-contexts-1us.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/shard-tglb6/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@kms:
- shard-tglb: [FAIL][166] ([i915#232]) -> [PASS][
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21947/index.html
[-- Attachment #2: Type: text/html, Size: 33613 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: split out vlv sideband registers from i915_reg.h
2022-01-10 9:57 ` [Intel-gfx] [PATCH 2/4] drm/i915: split out vlv sideband " Jani Nikula
@ 2022-01-10 14:32 ` Jani Nikula
0 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-01-10 14:32 UTC (permalink / raw)
To: intel-gfx
On Mon, 10 Jan 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> Add a dedicated file vlv_sideband_reg.h for the VLV/CHV sideband
> registers. The sideband registers macros are needed by the same files
> that need vlv_sideband.h, so include the definitions from there.
>
> v2: Fix copyright year (Matt)
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Pushed the first two to drm-intel-next, thanks for the review.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 171 ----------------------
> drivers/gpu/drm/i915/vlv_sideband.h | 2 +
> drivers/gpu/drm/i915/vlv_sideband_reg.h | 180 ++++++++++++++++++++++++
> 3 files changed, 182 insertions(+), 171 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/vlv_sideband_reg.h
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index baa0b9e6acb2..61ade07068c8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1166,177 +1166,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
>
> -/* See configdb bunit SB addr map */
> -#define BUNIT_REG_BISOC 0x11
> -
> -/* PUNIT_REG_*SSPM0 */
> -#define _SSPM0_SSC(val) ((val) << 0)
> -#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
> -#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
> -#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
> -#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
> -#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
> -#define _SSPM0_SSS(val) ((val) << 24)
> -#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
> -#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
> -#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
> -#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
> -#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
> -
> -/* PUNIT_REG_*SSPM1 */
> -#define SSPM1_FREQSTAT_SHIFT 24
> -#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
> -#define SSPM1_FREQGUAR_SHIFT 8
> -#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
> -#define SSPM1_FREQ_SHIFT 0
> -#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
> -
> -#define PUNIT_REG_VEDSSPM0 0x32
> -#define PUNIT_REG_VEDSSPM1 0x33
> -
> -#define PUNIT_REG_DSPSSPM 0x36
> -#define DSPFREQSTAT_SHIFT_CHV 24
> -#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
> -#define DSPFREQGUAR_SHIFT_CHV 8
> -#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
> -#define DSPFREQSTAT_SHIFT 30
> -#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
> -#define DSPFREQGUAR_SHIFT 14
> -#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
> -#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
> -#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
> -#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
> -#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
> -#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
> -#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
> -#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
> -#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
> -#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
> -#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
> -#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
> -#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
> -#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
> -#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
> -#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
> -
> -#define PUNIT_REG_ISPSSPM0 0x39
> -#define PUNIT_REG_ISPSSPM1 0x3a
> -
> -#define PUNIT_REG_PWRGT_CTRL 0x60
> -#define PUNIT_REG_PWRGT_STATUS 0x61
> -#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
> -#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
> -#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
> -#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
> -#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
> -
> -#define PUNIT_PWGT_IDX_RENDER 0
> -#define PUNIT_PWGT_IDX_MEDIA 1
> -#define PUNIT_PWGT_IDX_DISP2D 3
> -#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
> -#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
> -#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
> -#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
> -#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
> -#define PUNIT_PWGT_IDX_DPIO_RX0 10
> -#define PUNIT_PWGT_IDX_DPIO_RX1 11
> -#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
> -
> -#define PUNIT_REG_GPU_LFM 0xd3
> -#define PUNIT_REG_GPU_FREQ_REQ 0xd4
> -#define PUNIT_REG_GPU_FREQ_STS 0xd8
> -#define GPLLENABLE (1 << 4)
> -#define GENFREQSTATUS (1 << 0)
> -#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
> -#define PUNIT_REG_CZ_TIMESTAMP 0xce
> -
> -#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> -#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
> -
> -#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
> -#define FB_GFX_FREQ_FUSE_MASK 0xff
> -#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
> -#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
> -#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
> -
> -#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
> -#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
> -
> -#define PUNIT_REG_DDR_SETUP2 0x139
> -#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
> -#define FORCE_DDR_LOW_FREQ (1 << 1)
> -#define FORCE_DDR_HIGH_FREQ (1 << 0)
> -
> -#define PUNIT_GPU_STATUS_REG 0xdb
> -#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
> -#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
> -#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
> -#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
> -
> -#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
> -#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
> -#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
> -
> -#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
> -#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
> -#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
> -#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
> -#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
> -#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
> -#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
> -#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
> -#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
> -#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
> -
> -#define VLV_TURBO_SOC_OVERRIDE 0x04
> -#define VLV_OVERRIDE_EN 1
> -#define VLV_SOC_TDP_EN (1 << 1)
> -#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
> -#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
> -
> -/* vlv2 north clock has */
> -#define CCK_FUSE_REG 0x8
> -#define CCK_FUSE_HPLL_FREQ_MASK 0x3
> -#define CCK_REG_DSI_PLL_FUSE 0x44
> -#define CCK_REG_DSI_PLL_CONTROL 0x48
> -#define DSI_PLL_VCO_EN (1 << 31)
> -#define DSI_PLL_LDO_GATE (1 << 30)
> -#define DSI_PLL_P1_POST_DIV_SHIFT 17
> -#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
> -#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
> -#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
> -#define DSI_PLL_MUX_MASK (3 << 9)
> -#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
> -#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
> -#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
> -#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
> -#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
> -#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
> -#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
> -#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
> -#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
> -#define DSI_PLL_LOCK (1 << 0)
> -#define CCK_REG_DSI_PLL_DIVIDER 0x4c
> -#define DSI_PLL_LFSR (1 << 31)
> -#define DSI_PLL_FRACTION_EN (1 << 30)
> -#define DSI_PLL_FRAC_COUNTER_SHIFT 27
> -#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
> -#define DSI_PLL_USYNC_CNT_SHIFT 18
> -#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
> -#define DSI_PLL_N1_DIV_SHIFT 16
> -#define DSI_PLL_N1_DIV_MASK (3 << 16)
> -#define DSI_PLL_M1_DIV_SHIFT 0
> -#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
> -#define CCK_CZ_CLOCK_CONTROL 0x62
> -#define CCK_GPLL_CLOCK_CONTROL 0x67
> -#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
> -#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
> -#define CCK_TRUNK_FORCE_ON (1 << 17)
> -#define CCK_TRUNK_FORCE_OFF (1 << 16)
> -#define CCK_FREQUENCY_STATUS (0x1f << 8)
> -#define CCK_FREQUENCY_STATUS_SHIFT 8
> -#define CCK_FREQUENCY_VALUES (0x1f << 0)
> -
> /* DPIO registers */
> #define DPIO_DEVFN 0
>
> diff --git a/drivers/gpu/drm/i915/vlv_sideband.h b/drivers/gpu/drm/i915/vlv_sideband.h
> index d7732f612e7f..9ce283d96b80 100644
> --- a/drivers/gpu/drm/i915/vlv_sideband.h
> +++ b/drivers/gpu/drm/i915/vlv_sideband.h
> @@ -9,6 +9,8 @@
> #include <linux/bitops.h>
> #include <linux/types.h>
>
> +#include "vlv_sideband_reg.h"
> +
> enum pipe;
> struct drm_i915_private;
>
> diff --git a/drivers/gpu/drm/i915/vlv_sideband_reg.h b/drivers/gpu/drm/i915/vlv_sideband_reg.h
> new file mode 100644
> index 000000000000..b7fbff3d0409
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/vlv_sideband_reg.h
> @@ -0,0 +1,180 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef _VLV_SIDEBAND_REG_H_
> +#define _VLV_SIDEBAND_REG_H_
> +
> +/* See configdb bunit SB addr map */
> +#define BUNIT_REG_BISOC 0x11
> +
> +/* PUNIT_REG_*SSPM0 */
> +#define _SSPM0_SSC(val) ((val) << 0)
> +#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
> +#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
> +#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
> +#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
> +#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
> +#define _SSPM0_SSS(val) ((val) << 24)
> +#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
> +#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
> +#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
> +#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
> +#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
> +
> +/* PUNIT_REG_*SSPM1 */
> +#define SSPM1_FREQSTAT_SHIFT 24
> +#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
> +#define SSPM1_FREQGUAR_SHIFT 8
> +#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
> +#define SSPM1_FREQ_SHIFT 0
> +#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
> +
> +#define PUNIT_REG_VEDSSPM0 0x32
> +#define PUNIT_REG_VEDSSPM1 0x33
> +
> +#define PUNIT_REG_DSPSSPM 0x36
> +#define DSPFREQSTAT_SHIFT_CHV 24
> +#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
> +#define DSPFREQGUAR_SHIFT_CHV 8
> +#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
> +#define DSPFREQSTAT_SHIFT 30
> +#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
> +#define DSPFREQGUAR_SHIFT 14
> +#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
> +#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
> +#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
> +#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
> +#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
> +#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
> +#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
> +#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
> +#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
> +#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
> +#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
> +#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
> +#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
> +#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
> +#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
> +#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
> +
> +#define PUNIT_REG_ISPSSPM0 0x39
> +#define PUNIT_REG_ISPSSPM1 0x3a
> +
> +#define PUNIT_REG_PWRGT_CTRL 0x60
> +#define PUNIT_REG_PWRGT_STATUS 0x61
> +#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
> +#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
> +#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
> +#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
> +#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
> +
> +#define PUNIT_PWGT_IDX_RENDER 0
> +#define PUNIT_PWGT_IDX_MEDIA 1
> +#define PUNIT_PWGT_IDX_DISP2D 3
> +#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
> +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
> +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
> +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
> +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
> +#define PUNIT_PWGT_IDX_DPIO_RX0 10
> +#define PUNIT_PWGT_IDX_DPIO_RX1 11
> +#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
> +
> +#define PUNIT_REG_GPU_LFM 0xd3
> +#define PUNIT_REG_GPU_FREQ_REQ 0xd4
> +#define PUNIT_REG_GPU_FREQ_STS 0xd8
> +#define GPLLENABLE (1 << 4)
> +#define GENFREQSTATUS (1 << 0)
> +#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
> +#define PUNIT_REG_CZ_TIMESTAMP 0xce
> +
> +#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> +#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
> +
> +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
> +#define FB_GFX_FREQ_FUSE_MASK 0xff
> +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
> +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
> +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
> +
> +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
> +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
> +
> +#define PUNIT_REG_DDR_SETUP2 0x139
> +#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
> +#define FORCE_DDR_LOW_FREQ (1 << 1)
> +#define FORCE_DDR_HIGH_FREQ (1 << 0)
> +
> +#define PUNIT_GPU_STATUS_REG 0xdb
> +#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
> +#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
> +#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
> +#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
> +
> +#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
> +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
> +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
> +
> +#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
> +#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
> +#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
> +#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
> +#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
> +#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
> +#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
> +#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
> +#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
> +#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
> +
> +#define VLV_TURBO_SOC_OVERRIDE 0x04
> +#define VLV_OVERRIDE_EN 1
> +#define VLV_SOC_TDP_EN (1 << 1)
> +#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
> +#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
> +
> +/* vlv2 north clock has */
> +#define CCK_FUSE_REG 0x8
> +#define CCK_FUSE_HPLL_FREQ_MASK 0x3
> +#define CCK_REG_DSI_PLL_FUSE 0x44
> +#define CCK_REG_DSI_PLL_CONTROL 0x48
> +#define DSI_PLL_VCO_EN (1 << 31)
> +#define DSI_PLL_LDO_GATE (1 << 30)
> +#define DSI_PLL_P1_POST_DIV_SHIFT 17
> +#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
> +#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
> +#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
> +#define DSI_PLL_MUX_MASK (3 << 9)
> +#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
> +#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
> +#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
> +#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
> +#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
> +#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
> +#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
> +#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
> +#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
> +#define DSI_PLL_LOCK (1 << 0)
> +#define CCK_REG_DSI_PLL_DIVIDER 0x4c
> +#define DSI_PLL_LFSR (1 << 31)
> +#define DSI_PLL_FRACTION_EN (1 << 30)
> +#define DSI_PLL_FRAC_COUNTER_SHIFT 27
> +#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
> +#define DSI_PLL_USYNC_CNT_SHIFT 18
> +#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
> +#define DSI_PLL_N1_DIV_SHIFT 16
> +#define DSI_PLL_N1_DIV_MASK (3 << 16)
> +#define DSI_PLL_M1_DIV_SHIFT 0
> +#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
> +#define CCK_CZ_CLOCK_CONTROL 0x62
> +#define CCK_GPLL_CLOCK_CONTROL 0x67
> +#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
> +#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
> +#define CCK_TRUNK_FORCE_ON (1 << 17)
> +#define CCK_TRUNK_FORCE_OFF (1 << 16)
> +#define CCK_FREQUENCY_STATUS (0x1f << 8)
> +#define CCK_FREQUENCY_STATUS_SHIFT 8
> +#define CCK_FREQUENCY_VALUES (0x1f << 0)
> +
> +#endif /* _VLV_SIDEBAND_REG_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-01-10 9:57 ` [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h Jani Nikula
@ 2022-01-10 16:03 ` Ville Syrjälä
2022-01-11 8:55 ` Jani Nikula
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2022-01-10 16:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Jan 10, 2022 at 11:57:39AM +0200, Jani Nikula wrote:
> The video/vga.h has macros for the VGA registers. Switch to use them.
>
> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vga.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
> index fa779f7ea415..43c12036c1fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_vga.c
> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
> @@ -7,6 +7,7 @@
> #include <linux/vgaarb.h>
>
> #include <drm/i915_drm.h>
> +#include <video/vga.h>
>
> #include "i915_drv.h"
> #include "intel_de.h"
> @@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
>
> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> - outb(SR01, VGA_SR_INDEX);
> - sr1 = inb(VGA_SR_DATA);
> - outb(sr1 | 1 << 5, VGA_SR_DATA);
> + outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I);
Not a huge fan of some of these defines since now I have
no idea what register this is selecting.
> + sr1 = inb(VGA_SEQ_D);
> + outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D);
> vga_put(pdev, VGA_RSRC_LEGACY_IO);
> udelay(300);
>
> @@ -92,7 +93,7 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915)
> * and error messages.
> */
> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> - outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
> + outb(inb(VGA_MIS_R), VGA_MIS_W);
> vga_put(pdev, VGA_RSRC_LEGACY_IO);
> }
>
> --
> 2.30.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-01-10 16:03 ` Ville Syrjälä
@ 2022-01-11 8:55 ` Jani Nikula
2022-01-11 16:14 ` Lucas De Marchi
2022-01-12 13:24 ` Ville Syrjälä
0 siblings, 2 replies; 18+ messages in thread
From: Jani Nikula @ 2022-01-11 8:55 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, 10 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Jan 10, 2022 at 11:57:39AM +0200, Jani Nikula wrote:
>> The video/vga.h has macros for the VGA registers. Switch to use them.
>>
>> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_vga.c | 9 +++++----
>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
>> index fa779f7ea415..43c12036c1fa 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vga.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
>> @@ -7,6 +7,7 @@
>> #include <linux/vgaarb.h>
>>
>> #include <drm/i915_drm.h>
>> +#include <video/vga.h>
>>
>> #include "i915_drv.h"
>> #include "intel_de.h"
>> @@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
>>
>> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
>> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
>> - outb(SR01, VGA_SR_INDEX);
>> - sr1 = inb(VGA_SR_DATA);
>> - outb(sr1 | 1 << 5, VGA_SR_DATA);
>> + outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I);
>
> Not a huge fan of some of these defines since now I have
> no idea what register this is selecting.
It's a bit silly that we have our own macros for this stuff, but I get
the point. Took me a while to figure the changes out because the macros
in video/vga.h aren't even grouped in a helpful way.
I guess you'd prefer patch [1] over patches 3-4 in this series then? For
me the main goal is to just reduce the size of i915_reg.h.
BR,
Jani.
[1] https://patchwork.freedesktop.org/patch/msgid/20220107094951.96181-2-jani.nikula@intel.com
>
>> + sr1 = inb(VGA_SEQ_D);
>> + outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D);
>> vga_put(pdev, VGA_RSRC_LEGACY_IO);
>> udelay(300);
>>
>> @@ -92,7 +93,7 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915)
>> * and error messages.
>> */
>> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
>> - outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
>> + outb(inb(VGA_MIS_R), VGA_MIS_W);
>> vga_put(pdev, VGA_RSRC_LEGACY_IO);
>> }
>>
>> --
>> 2.30.2
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-01-11 8:55 ` Jani Nikula
@ 2022-01-11 16:14 ` Lucas De Marchi
2022-01-11 16:19 ` Jani Nikula
2022-01-12 13:24 ` Ville Syrjälä
1 sibling, 1 reply; 18+ messages in thread
From: Lucas De Marchi @ 2022-01-11 16:14 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Jan 11, 2022 at 10:55:44AM +0200, Jani Nikula wrote:
>On Mon, 10 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> On Mon, Jan 10, 2022 at 11:57:39AM +0200, Jani Nikula wrote:
>>> The video/vga.h has macros for the VGA registers. Switch to use them.
>>>
>>> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_vga.c | 9 +++++----
>>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
>>> index fa779f7ea415..43c12036c1fa 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vga.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
>>> @@ -7,6 +7,7 @@
>>> #include <linux/vgaarb.h>
>>>
>>> #include <drm/i915_drm.h>
>>> +#include <video/vga.h>
>>>
>>> #include "i915_drv.h"
>>> #include "intel_de.h"
>>> @@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
>>>
>>> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
>>> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
>>> - outb(SR01, VGA_SR_INDEX);
>>> - sr1 = inb(VGA_SR_DATA);
>>> - outb(sr1 | 1 << 5, VGA_SR_DATA);
>>> + outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I);
>>
>> Not a huge fan of some of these defines since now I have
>> no idea what register this is selecting.
>
>It's a bit silly that we have our own macros for this stuff, but I get
>the point. Took me a while to figure the changes out because the macros
>in video/vga.h aren't even grouped in a helpful way.
>
>I guess you'd prefer patch [1] over patches 3-4 in this series then? For
>me the main goal is to just reduce the size of i915_reg.h.
alternatively, to patch video/vga.h to make it pretty?
Lucas De Marchi
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-01-11 16:14 ` Lucas De Marchi
@ 2022-01-11 16:19 ` Jani Nikula
2022-01-11 16:37 ` Lucas De Marchi
0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2022-01-11 16:19 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, 11 Jan 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Tue, Jan 11, 2022 at 10:55:44AM +0200, Jani Nikula wrote:
>>On Mon, 10 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>>> On Mon, Jan 10, 2022 at 11:57:39AM +0200, Jani Nikula wrote:
>>>> The video/vga.h has macros for the VGA registers. Switch to use them.
>>>>
>>>> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
>>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_vga.c | 9 +++++----
>>>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
>>>> index fa779f7ea415..43c12036c1fa 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vga.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
>>>> @@ -7,6 +7,7 @@
>>>> #include <linux/vgaarb.h>
>>>>
>>>> #include <drm/i915_drm.h>
>>>> +#include <video/vga.h>
>>>>
>>>> #include "i915_drv.h"
>>>> #include "intel_de.h"
>>>> @@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
>>>>
>>>> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
>>>> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
>>>> - outb(SR01, VGA_SR_INDEX);
>>>> - sr1 = inb(VGA_SR_DATA);
>>>> - outb(sr1 | 1 << 5, VGA_SR_DATA);
>>>> + outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I);
>>>
>>> Not a huge fan of some of these defines since now I have
>>> no idea what register this is selecting.
>>
>>It's a bit silly that we have our own macros for this stuff, but I get
>>the point. Took me a while to figure the changes out because the macros
>>in video/vga.h aren't even grouped in a helpful way.
>>
>>I guess you'd prefer patch [1] over patches 3-4 in this series then? For
>>me the main goal is to just reduce the size of i915_reg.h.
>
> alternatively, to patch video/vga.h to make it pretty?
If it's enough to just rearrange the stuff, maybe. But if it means
renames, I'm not going to touch a big pile of ancient fb/vga drivers to
chase this one.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-01-11 16:19 ` Jani Nikula
@ 2022-01-11 16:37 ` Lucas De Marchi
0 siblings, 0 replies; 18+ messages in thread
From: Lucas De Marchi @ 2022-01-11 16:37 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Jan 11, 2022 at 06:19:10PM +0200, Jani Nikula wrote:
>On Tue, 11 Jan 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> On Tue, Jan 11, 2022 at 10:55:44AM +0200, Jani Nikula wrote:
>>>On Mon, 10 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>>>> On Mon, Jan 10, 2022 at 11:57:39AM +0200, Jani Nikula wrote:
>>>>> The video/vga.h has macros for the VGA registers. Switch to use them.
>>>>>
>>>>> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
>>>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_vga.c | 9 +++++----
>>>>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
>>>>> index fa779f7ea415..43c12036c1fa 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_vga.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
>>>>> @@ -7,6 +7,7 @@
>>>>> #include <linux/vgaarb.h>
>>>>>
>>>>> #include <drm/i915_drm.h>
>>>>> +#include <video/vga.h>
>>>>>
>>>>> #include "i915_drv.h"
>>>>> #include "intel_de.h"
>>>>> @@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
>>>>>
>>>>> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
>>>>> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
>>>>> - outb(SR01, VGA_SR_INDEX);
>>>>> - sr1 = inb(VGA_SR_DATA);
>>>>> - outb(sr1 | 1 << 5, VGA_SR_DATA);
>>>>> + outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I);
>>>>
>>>> Not a huge fan of some of these defines since now I have
>>>> no idea what register this is selecting.
>>>
>>>It's a bit silly that we have our own macros for this stuff, but I get
>>>the point. Took me a while to figure the changes out because the macros
>>>in video/vga.h aren't even grouped in a helpful way.
>>>
>>>I guess you'd prefer patch [1] over patches 3-4 in this series then? For
>>>me the main goal is to just reduce the size of i915_reg.h.
>>
>> alternatively, to patch video/vga.h to make it pretty?
>
>If it's enough to just rearrange the stuff, maybe. But if it means
>renames, I'm not going to touch a big pile of ancient fb/vga drivers to
>chase this one.
I think it would be ok to add them as aliases to the names used in
other places. Then the other places can be converted later if at all.
But not a strong opinion... up to you, Ville and Matt.
Lucas De Marchi
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-01-11 8:55 ` Jani Nikula
2022-01-11 16:14 ` Lucas De Marchi
@ 2022-01-12 13:24 ` Ville Syrjälä
2022-02-02 9:17 ` Jani Nikula
1 sibling, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2022-01-12 13:24 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Jan 11, 2022 at 10:55:44AM +0200, Jani Nikula wrote:
> On Mon, 10 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Mon, Jan 10, 2022 at 11:57:39AM +0200, Jani Nikula wrote:
> >> The video/vga.h has macros for the VGA registers. Switch to use them.
> >>
> >> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_vga.c | 9 +++++----
> >> 1 file changed, 5 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
> >> index fa779f7ea415..43c12036c1fa 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vga.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
> >> @@ -7,6 +7,7 @@
> >> #include <linux/vgaarb.h>
> >>
> >> #include <drm/i915_drm.h>
> >> +#include <video/vga.h>
> >>
> >> #include "i915_drv.h"
> >> #include "intel_de.h"
> >> @@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
> >>
> >> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
> >> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> >> - outb(SR01, VGA_SR_INDEX);
> >> - sr1 = inb(VGA_SR_DATA);
> >> - outb(sr1 | 1 << 5, VGA_SR_DATA);
> >> + outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I);
> >
> > Not a huge fan of some of these defines since now I have
> > no idea what register this is selecting.
>
> It's a bit silly that we have our own macros for this stuff, but I get
> the point. Took me a while to figure the changes out because the macros
> in video/vga.h aren't even grouped in a helpful way.
>
> I guess you'd prefer patch [1] over patches 3-4 in this series then? For
> me the main goal is to just reduce the size of i915_reg.h.
I guess another option is to go with this and just
s/VGA_SEQ_CLOCK_MODE/0x01/ or something. I think the rest
of the defines are probably clear enough.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-01-12 13:24 ` Ville Syrjälä
@ 2022-02-02 9:17 ` Jani Nikula
2022-02-02 10:22 ` Ville Syrjälä
0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2022-02-02 9:17 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, 12 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Jan 11, 2022 at 10:55:44AM +0200, Jani Nikula wrote:
>> On Mon, 10 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> > On Mon, Jan 10, 2022 at 11:57:39AM +0200, Jani Nikula wrote:
>> >> The video/vga.h has macros for the VGA registers. Switch to use them.
>> >>
>> >> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
>> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/display/intel_vga.c | 9 +++++----
>> >> 1 file changed, 5 insertions(+), 4 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
>> >> index fa779f7ea415..43c12036c1fa 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_vga.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
>> >> @@ -7,6 +7,7 @@
>> >> #include <linux/vgaarb.h>
>> >>
>> >> #include <drm/i915_drm.h>
>> >> +#include <video/vga.h>
>> >>
>> >> #include "i915_drv.h"
>> >> #include "intel_de.h"
>> >> @@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
>> >>
>> >> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
>> >> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
>> >> - outb(SR01, VGA_SR_INDEX);
>> >> - sr1 = inb(VGA_SR_DATA);
>> >> - outb(sr1 | 1 << 5, VGA_SR_DATA);
>> >> + outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I);
>> >
>> > Not a huge fan of some of these defines since now I have
>> > no idea what register this is selecting.
>>
>> It's a bit silly that we have our own macros for this stuff, but I get
>> the point. Took me a while to figure the changes out because the macros
>> in video/vga.h aren't even grouped in a helpful way.
>>
>> I guess you'd prefer patch [1] over patches 3-4 in this series then? For
>> me the main goal is to just reduce the size of i915_reg.h.
>
> I guess another option is to go with this and just
> s/VGA_SEQ_CLOCK_MODE/0x01/ or something. I think the rest
> of the defines are probably clear enough.
I dropped the ball here a bit. If I respin the same patches, but with
the above line changed to one of these, is it okay? Which do you prefer?
1) outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I); /* SR01 */
2) #define SR01 VGA_SEQ_CLOCK_MODE
outb(SR01, VGA_SEQ_I);
3) outb(0x01, VGA_SEQ_I);
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-02-02 9:17 ` Jani Nikula
@ 2022-02-02 10:22 ` Ville Syrjälä
2022-02-02 11:25 ` Jani Nikula
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2022-02-02 10:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Feb 02, 2022 at 11:17:11AM +0200, Jani Nikula wrote:
> On Wed, 12 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Tue, Jan 11, 2022 at 10:55:44AM +0200, Jani Nikula wrote:
> >> On Mon, 10 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >> > On Mon, Jan 10, 2022 at 11:57:39AM +0200, Jani Nikula wrote:
> >> >> The video/vga.h has macros for the VGA registers. Switch to use them.
> >> >>
> >> >> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
> >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> >> ---
> >> >> drivers/gpu/drm/i915/display/intel_vga.c | 9 +++++----
> >> >> 1 file changed, 5 insertions(+), 4 deletions(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
> >> >> index fa779f7ea415..43c12036c1fa 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_vga.c
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
> >> >> @@ -7,6 +7,7 @@
> >> >> #include <linux/vgaarb.h>
> >> >>
> >> >> #include <drm/i915_drm.h>
> >> >> +#include <video/vga.h>
> >> >>
> >> >> #include "i915_drv.h"
> >> >> #include "intel_de.h"
> >> >> @@ -34,9 +35,9 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
> >> >>
> >> >> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
> >> >> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> >> >> - outb(SR01, VGA_SR_INDEX);
> >> >> - sr1 = inb(VGA_SR_DATA);
> >> >> - outb(sr1 | 1 << 5, VGA_SR_DATA);
> >> >> + outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I);
> >> >
> >> > Not a huge fan of some of these defines since now I have
> >> > no idea what register this is selecting.
> >>
> >> It's a bit silly that we have our own macros for this stuff, but I get
> >> the point. Took me a while to figure the changes out because the macros
> >> in video/vga.h aren't even grouped in a helpful way.
> >>
> >> I guess you'd prefer patch [1] over patches 3-4 in this series then? For
> >> me the main goal is to just reduce the size of i915_reg.h.
> >
> > I guess another option is to go with this and just
> > s/VGA_SEQ_CLOCK_MODE/0x01/ or something. I think the rest
> > of the defines are probably clear enough.
>
> I dropped the ball here a bit. If I respin the same patches, but with
> the above line changed to one of these, is it okay? Which do you prefer?
>
> 1) outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I); /* SR01 */
>
> 2) #define SR01 VGA_SEQ_CLOCK_MODE
> outb(SR01, VGA_SEQ_I);
>
> 3) outb(0x01, VGA_SEQ_I);
3 seems like the best option of these.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h
2022-02-02 10:22 ` Ville Syrjälä
@ 2022-02-02 11:25 ` Jani Nikula
0 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-02-02 11:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, 02 Feb 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> I dropped the ball here a bit. If I respin the same patches, but with
>> the above line changed to one of these, is it okay? Which do you prefer?
>>
>> 1) outb(VGA_SEQ_CLOCK_MODE, VGA_SEQ_I); /* SR01 */
>>
>> 2) #define SR01 VGA_SEQ_CLOCK_MODE
>> outb(SR01, VGA_SEQ_I);
>>
>> 3) outb(0x01, VGA_SEQ_I);
>
> 3 seems like the best option of these.
Thanks, v2 on the list.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-02-02 11:25 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-10 9:57 [Intel-gfx] [PATCH 1/4] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
2022-01-10 9:57 ` [Intel-gfx] [PATCH 2/4] drm/i915: split out vlv sideband " Jani Nikula
2022-01-10 14:32 ` Jani Nikula
2022-01-10 9:57 ` [Intel-gfx] [PATCH 3/4] drm/i915/vga: switch to use VGA definitions from video/vga.h Jani Nikula
2022-01-10 16:03 ` Ville Syrjälä
2022-01-11 8:55 ` Jani Nikula
2022-01-11 16:14 ` Lucas De Marchi
2022-01-11 16:19 ` Jani Nikula
2022-01-11 16:37 ` Lucas De Marchi
2022-01-12 13:24 ` Ville Syrjälä
2022-02-02 9:17 ` Jani Nikula
2022-02-02 10:22 ` Ville Syrjälä
2022-02-02 11:25 ` Jani Nikula
2022-01-10 9:57 ` [Intel-gfx] [PATCH 4/4] drm/i915: remove VGA register definitions Jani Nikula
2022-01-10 10:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: split out PCI config space registers from i915_reg.h Patchwork
2022-01-10 10:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-10 11:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-10 13:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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