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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 2/7] drm/i915: Parameterize PWRCTX_MAXCNT
Date: Mon, 10 Jan 2022 13:06:49 +0200	[thread overview]
Message-ID: <87pmozalyu.fsf@intel.com> (raw)
In-Reply-To: <20220108044055.3123418-3-matthew.d.roper@intel.com>

On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> Rather than having separate definitions for each engine, create a single
> parameterized macro that takes the engine base offset.  This will also
> ensure we get to the proper offset if we ever need to use these
> registers on newer platforms (where the media engine offsets have
> changed).
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h     | 6 +-----
>  2 files changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index c3155ee58689..45891e6f0b98 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -449,10 +449,10 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
>  		enable_rc6 = false;
>  	}
>  
> -	if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
> -	      (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
> -	      (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
> -	      (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
> +	if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
> +	      (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
> +	      (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
> +	      (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
>  		drm_dbg(&i915->drm,
>  			"Engine Idle wait time not set properly.\n");
>  		enable_rc6 = false;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 86e459010465..23330faecf07 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9297,11 +9297,7 @@ enum {
>  #define	   RC6_CTX_IN_DRAM			(1 << 0)
>  #define  RC6_CTX_BASE				_MMIO(0xD48)
>  #define    RC6_CTX_BASE_MASK			0xFFFFFFF0
> -#define  PWRCTX_MAXCNT_RCSUNIT			_MMIO(0x2054)
> -#define  PWRCTX_MAXCNT_VCSUNIT0			_MMIO(0x12054)
> -#define  PWRCTX_MAXCNT_BCSUNIT			_MMIO(0x22054)
> -#define  PWRCTX_MAXCNT_VECSUNIT			_MMIO(0x1A054)
> -#define  PWRCTX_MAXCNT_VCSUNIT1			_MMIO(0x1C054)
> +#define  PWRCTX_MAXCNT(base)			_MMIO((base) + 0x54)
>  #define    IDLE_TIME_MASK			0xFFFFF
>  #define  FORCEWAKE				_MMIO(0xA18C)
>  #define  FORCEWAKE_VLV				_MMIO(0x1300b0)

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-01-10 11:06 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-08  4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
2022-01-08  4:40 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
2022-01-10 11:20   ` Jani Nikula
2022-01-08  4:40 ` [Intel-gfx] [PATCH v2 2/7] drm/i915: Parameterize PWRCTX_MAXCNT Matt Roper
2022-01-10 11:06   ` Jani Nikula [this message]
2022-01-08  4:40 ` [Intel-gfx] [PATCH v2 3/7] drm/i915: Parameterize ECOSKPD Matt Roper
2022-01-10 11:10   ` Jani Nikula
2022-01-08  4:40 ` [Intel-gfx] [PATCH v2 4/7] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
2022-01-10 11:14   ` Jani Nikula
2022-01-08  4:40 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
2022-01-10 11:15   ` Jani Nikula
2022-01-08  4:40 ` [Intel-gfx] [PATCH v2 6/7] drm/i915/gt: Move engine registers to their own header Matt Roper
2022-01-10 10:59   ` Jani Nikula
2022-01-08  4:40 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Move SNPS PHY " Matt Roper
2022-01-10 11:02   ` Jani Nikula
2022-01-10 11:03     ` Jani Nikula
2022-01-08  5:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev2) Patchwork
2022-01-08  5:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-08  5:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-08  7:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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