From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ECD7C433F5 for ; Tue, 21 Sep 2021 08:45:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1568261131 for ; Tue, 21 Sep 2021 08:45:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1568261131 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 562536E916; Tue, 21 Sep 2021 08:45:01 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id A24736E916; Tue, 21 Sep 2021 08:44:59 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10113"; a="284326439" X-IronPort-AV: E=Sophos;i="5.85,310,1624345200"; d="scan'208";a="284326439" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2021 01:44:58 -0700 X-IronPort-AV: E=Sophos;i="5.85,310,1624345200"; d="scan'208";a="556850956" Received: from unknown (HELO localhost) ([10.251.218.108]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2021 01:44:56 -0700 From: Jani Nikula To: Ville =?utf-8?B?U3lyasOkbMOk?= Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, manasi.d.navare@intel.com Subject: Re: [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: Date: Tue, 21 Sep 2021 11:44:53 +0300 Message-ID: <87pmt2tj0a.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, 17 Sep 2021, Ville Syrj=C3=A4l=C3=A4 wrote: > On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: >> There's a new register pair for 128b/132b mode where you need to set the >> pixel clock in Hz. >>=20 >> v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper >>=20 >> Bspec: 54128 >> Signed-off-by: Jani Nikula > > Reviewed-by: Ville Syrj=C3=A4l=C3=A4 Thanks for the reviews, pushed up to and including this one. BR, Jani. > >> --- >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >>=20 >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/d= rm/i915/display/intel_dp_mst.c >> index d104441344c0..97af19fd9780 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic= _state *state, >>=20=20 >> clear_act_sent(encoder, pipe_config); >>=20=20 >> + if (intel_dp_is_uhbr(pipe_config)) { >> + const struct drm_display_mode *adjusted_mode =3D >> + &pipe_config->hw.adjusted_mode; >> + u64 crtc_clock_hz =3D KHz(adjusted_mode->crtc_clock); >> + >> + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transco= der), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); >> + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcod= er), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); >> + } >> + >> intel_ddi_enable_transcoder_func(encoder, pipe_config); >>=20=20 >> intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, >> --=20 >> 2.30.2 --=20 Jani Nikula, Intel Open Source Graphics Center From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C12A0C433EF for ; Tue, 21 Sep 2021 08:45:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7F81661131 for ; Tue, 21 Sep 2021 08:45:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7F81661131 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E45A6E917; Tue, 21 Sep 2021 08:45:01 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id A24736E916; Tue, 21 Sep 2021 08:44:59 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10113"; a="284326439" X-IronPort-AV: E=Sophos;i="5.85,310,1624345200"; d="scan'208";a="284326439" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2021 01:44:58 -0700 X-IronPort-AV: E=Sophos;i="5.85,310,1624345200"; d="scan'208";a="556850956" Received: from unknown (HELO localhost) ([10.251.218.108]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2021 01:44:56 -0700 From: Jani Nikula To: Ville =?utf-8?B?U3lyasOkbMOk?= Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, manasi.d.navare@intel.com In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: Date: Tue, 21 Sep 2021 11:44:53 +0300 Message-ID: <87pmt2tj0a.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 17 Sep 2021, Ville Syrj=C3=A4l=C3=A4 wrote: > On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: >> There's a new register pair for 128b/132b mode where you need to set the >> pixel clock in Hz. >>=20 >> v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper >>=20 >> Bspec: 54128 >> Signed-off-by: Jani Nikula > > Reviewed-by: Ville Syrj=C3=A4l=C3=A4 Thanks for the reviews, pushed up to and including this one. BR, Jani. > >> --- >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >>=20 >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/d= rm/i915/display/intel_dp_mst.c >> index d104441344c0..97af19fd9780 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic= _state *state, >>=20=20 >> clear_act_sent(encoder, pipe_config); >>=20=20 >> + if (intel_dp_is_uhbr(pipe_config)) { >> + const struct drm_display_mode *adjusted_mode =3D >> + &pipe_config->hw.adjusted_mode; >> + u64 crtc_clock_hz =3D KHz(adjusted_mode->crtc_clock); >> + >> + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transco= der), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); >> + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcod= er), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); >> + } >> + >> intel_ddi_enable_transcoder_func(encoder, pipe_config); >>=20=20 >> intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, >> --=20 >> 2.30.2 --=20 Jani Nikula, Intel Open Source Graphics Center