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X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Hoist the computation of some TBFLAG_A32 bits that only apply to > M-profile under a single test for ARM_FEATURE_M. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/helper.c | 49 +++++++++++++++++++++------------------------ > 1 file changed, 23 insertions(+), 26 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d4303420da..296a4b2232 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -11194,6 +11194,29 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targ= et_ulong *pc, > > if (arm_feature(env, ARM_FEATURE_M)) { > flags =3D rebuild_hflags_m32(env, fp_el, mmu_idx); > + > + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && > + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) > + !=3D env->v7m.secure) { > + flags =3D FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1= ); > + } > + > + if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MAS= K) && > + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) = || > + (env->v7m.secure && > + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)= ))) { > + /* > + * ASPEN is set, but FPCA/SFPA indicate that there is no > + * active FP context; we must create a new FP context be= fore > + * executing any FP insn. > + */ > + flags =3D FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEED= ED, 1); > + } > + > + bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_M= ASK; > + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { > + flags =3D FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); > + } > } else { > flags =3D rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); > } > @@ -11233,32 +11256,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targ= et_ulong *pc, > } > } > > - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && > - FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) !=3D env->v7m.= secure) { > - flags =3D FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); > - } > - > - if (arm_feature(env, ARM_FEATURE_M) && > - (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && > - (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || > - (env->v7m.secure && > - !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { > - /* > - * ASPEN is set, but FPCA/SFPA indicate that there is no active > - * FP context; we must create a new FP context before executing > - * any FP insn. > - */ > - flags =3D FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); > - } > - > - if (arm_feature(env, ARM_FEATURE_M)) { > - bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; > - > - if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { > - flags =3D FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); > - } > - } > - > if (!arm_feature(env, ARM_FEATURE_M)) { > int target_el =3D arm_debug_target_el(env); -- Alex Benn=C3=A9e