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Fri, 3 Dec 2021 13:03:36 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7BFAAAE067; Fri, 3 Dec 2021 13:03:35 +0000 (GMT) Received: from localhost (unknown [9.211.34.214]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTPS; Fri, 3 Dec 2021 13:03:35 +0000 (GMT) From: Fabiano Rosas To: =?utf-8?Q?C=C3=A9dric?= Le Goater , Daniel Henrique Barboza , qemu-devel@nongnu.org Subject: Re: [PATCH v9 00/10] PMU-EBB support for PPC64 TCG In-Reply-To: <27d2eb41-f34a-5c2d-e1f1-977f08ac58d8@kaod.org> References: <20211201151734.654994-1-danielhb413@gmail.com> <27d2eb41-f34a-5c2d-e1f1-977f08ac58d8@kaod.org> Date: Fri, 03 Dec 2021 10:03:32 -0300 Message-ID: <87r1atj0wr.fsf@linux.ibm.com> Content-Type: text/plain; charset=utf-8 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 6eEMNbiOuaR1D_w8tKAqnBgGQAAcjMZQ X-Proofpoint-ORIG-GUID: w3LZR1iNyzcwvjshkEsjsDnQk7Eb-tYb Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-03_06,2021-12-02_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 spamscore=0 impostorscore=0 suspectscore=0 mlxscore=0 phishscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2112030082 Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, richard.henderson@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" C=C3=A9dric Le Goater writes: > Hello, > > On 12/1/21 16:17, Daniel Henrique Barboza wrote: >> Hi, >>=20 >> In this new version the most significant change is in patch 6, >> where a new hflag allows us to not call the instruction helper >> inside translate.c unless we're absolutely certain that there >> is an instruction count event being sampled and active in the >> PMU. This change turned out to be a big boost in performance >> in the PMU emulation overall, most notably when dealing with >> cycle events that were calling the helper needlessly. >>=20 >> This and all other changes were suggested by David in his review >> of the previous version. > > > patch 1-8 look good. I still have some questions on the exception > handling and how EBB are gated. > > I am asking to get the model right for the next step which should > be to modify the XIVE interrupt controller to generate External > EBB exceptions. > > One more comment, not for now, since the EBB patchset is nearly > ready. > > May be, it is time to think about introducing a per-CPU model > excp_handlers[] array indexed by POWERPC_EXCP_* exception > numbers and to duplicate some code for the sake of clarity. > > Fabiano, isn't it what you had in mind ? I had basically changed env->excp_vectors to be an array of objects of the kind: struct PPCInterrupt { Object parent; =20=20 int id; const char *name; target_ulong addr; ppc_intr_fn_t setup_regs; }; we would access it from powerpc_excp() with: intr =3D &env->excp_vectors[excp]; if (intr->setup_regs) { intr->setup_regs(cpu, intr, excp_model, ®s, &ignore); } I also had another series to move the exception models into QOM like this: struct PPCIntrModel { Object parent; =20=20 int id; const char *name; target_ulong hreset_vector; target_ulong ivor_mask; target_ulong ivpr_mask; target_ulong excp_prefix; PPCInterrupt excp_vectors[POWERPC_EXCP_NB]; }; struct PPCIntrModelClass { ObjectClass parent_class; =20=20 bool (*intr_little_endian)(CPUPPCState *env, bool hv); bool (*lpar_env_selection)(CPUPPCState *env); target_ulong (*filter_msr)(CPUPPCState *env); bool (*set_sixty_four_bit_mode)(CPUPPCState *env, target_ulong *msr); bool (*set_ail)(CPUPPCState *env, bool mmu_all_on, bool hv_escalation, bool hv, int *_ail); void (*prepare_tlb_miss)(PowerPCCPU *cpu, int excp, target_ulong *new= _msr, target_ulong *msr); void (*debug_software_tlb)(CPUPPCState *env, int excp); void (*init_excp)(PPCIntrModel *im); }; So the powerpc_excp() code would become: PPCIntrModel *intr_model =3D &env->im; PPCInterrupt *intr; ... intr =3D &intr_model->entry_points[excp]; if (!intr->setup_regs) { cpu_abort(cs, "Raised an exception without defined vector %d\n", excp); } regs.new_nip =3D intr->addr | intr_model->excp_prefix; intr->setup_regs(cpu, intr, intr_model, ®s, &ignore); I'll rebase it all and work on reducing some of the complexity around QOM, which was pointed out by David in the previous version: https://lists.nongnu.org/archive/html/qemu-ppc/2021-06/msg00140.html Any other suggestions are welcome. > > Thanks, > > C.