Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB

[Jani Nikula <jani.nikula@intel.com>]

On Tue, 19 Oct 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
>> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
>> 
>> Commit message goes here.
>> 
>> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
>> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
>> >  drivers/gpu/drm/i915/i915_reg.h        | 3 ++-
>> >  2 files changed, 3 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > index 9ee62707ec72..8c166f92f8bd 100644
>> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
>> >  	if (DISPLAY_VER(i915) == 13) {
>> >  		for_each_dsi_port(port, intel_dsi->ports)
>> >  			intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
>> > -				     TGL_DSI_CHKN_LSHS_GB, 0x4);
>> > +				     TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK);
>> 
>> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
>
> IMO the value should never be named that. It should be
> TGL_DSI_CHKN_LSHS_GB_<something>.

Alternatively,

#define TGL_DSI_CHKN_LSHS_GB(byte_clocks)		REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks))

and

intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
	     TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4));

?

We're using the value in a specific place that references a w/a, so the
magic 4 isn't too bad.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center