Re: [PATCH v12 2/8] drivers: clk: add fu740 support

From: Andreas Schwab <schwab@linux-m68k.org>
To: Green Wan <green.wan@sifive.com>
Cc: bmeng.cn@gmail.com,  Rick Chen <rick@andestech.com>,
	 Leo <ycliang@andestech.com>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Anup Patel <anup.patel@wdc.com>,
	Atish Patra <atish.patra@wdc.com>,
	 Pragnesh Patel <pragnesh.patel@sifive.com>,
	 Lukasz Majewski <lukma@denx.de>,
	u-boot@lists.denx.de
Subject: Re: [PATCH v12 2/8] drivers: clk: add fu740 support
Date: Tue, 15 Jun 2021 21:12:27 +0200	[thread overview]
Message-ID: <87sg1juelg.fsf@igel.home> (raw)
In-Reply-To: <20210527135215.370524-3-green.wan@sifive.com> (Green Wan's message of "Thu, 27 May 2021 06:52:08 -0700")

On Mai 27 2021, Green Wan wrote:

> +/* List of clock controls provided by the PRCI */
> +struct __prci_clock __prci_init_clocks_fu740[] = {
> +	[PRCI_CLK_COREPLL] = {
> +		.name = "corepll",
> +		.parent_name = "hfclk",
> +		.ops = &sifive_fu740_prci_wrpll_clk_ops,
> +		.pwd = &__prci_corepll_data,
> +	},
> +	[PRCI_CLK_DDRPLL] = {
> +		.name = "ddrpll",
> +		.parent_name = "hfclk",
> +		.ops = &sifive_fu740_prci_wrpll_clk_ops,
> +		.pwd = &__prci_ddrpll_data,
> +	},
> +	[PRCI_CLK_GEMGXLPLL] = {
> +		.name = "gemgxlpll",
> +		.parent_name = "hfclk",
> +		.ops = &sifive_fu740_prci_wrpll_clk_ops,
> +		.pwd = &__prci_gemgxlpll_data,
> +	},
> +	[PRCI_CLK_DVFSCOREPLL] = {
> +		.name = "dvfscorepll",
> +		.parent_name = "hfclk",
> +		.ops = &sifive_fu740_prci_wrpll_clk_ops,
> +		.pwd = &__prci_dvfscorepll_data,
> +	},
> +	[PRCI_CLK_HFPCLKPLL] = {
> +		.name = "hfpclkpll",
> +		.parent_name = "hfclk",
> +		.ops = &sifive_fu740_prci_wrpll_clk_ops,
> +		.pwd = &__prci_hfpclkpll_data,
> +	},
> +	[PRCI_CLK_CLTXPLL] = {
> +		.name = "cltxpll",
> +		.parent_name = "hfclk",
> +		.ops = &sifive_fu740_prci_wrpll_clk_ops,
> +		.pwd = &__prci_cltxpll_data,
> +	},
> +	[PRCI_CLK_TLCLK] = {
> +		.name = "tlclk",
> +		.parent_name = "corepll",
> +		.ops = &sifive_fu740_prci_tlclksel_clk_ops,
> +	},
> +	[PRCI_CLK_PCLK] = {
> +		.name = "pclk",
> +		.parent_name = "hfpclkpll",
> +		.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
> +	},
> +	[PRCI_CLK_PCIEAUX] {
> +		.name = "pciaux",

Shouldn't that be called "pcieaux"?

Andreas.

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Andreas Schwab, schwab@linux-m68k.org
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