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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: peter.maydell@linux.org, alex.bennee@linux.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v6 13/18] accel/tcg: Do not align tb->page_addr[0]
Date: Mon, 03 Oct 2022 15:59:49 +0100	[thread overview]
Message-ID: <87tu4llzno.fsf@linaro.org> (raw)
In-Reply-To: <cab82ec5-88c4-1624-8fff-a9f45a282470@linaro.org>


Richard Henderson <richard.henderson@linaro.org> writes:

> On 10/3/22 05:47, Alex Bennée wrote:
>> Richard Henderson <richard.henderson@linaro.org> writes:
>> 
>>> Let tb->page_addr[0] contain the offset within the page of the
>>> start of the translation block.  We need to recover this value
>>> anyway at various points, and it is easier to discard the page
>>> offset when it's not needed, which happens naturally via the
>>> existing find_page shift.
>>>
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>>   accel/tcg/cpu-exec.c      | 16 ++++++++--------
>>>   accel/tcg/cputlb.c        |  3 ++-
>>>   accel/tcg/translate-all.c |  9 +++++----
>>>   3 files changed, 15 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
>>> index 5f43b9769a..dd58a144a8 100644
>>> --- a/accel/tcg/cpu-exec.c
>>> +++ b/accel/tcg/cpu-exec.c
>>> @@ -174,7 +174,7 @@ struct tb_desc {
>>>       target_ulong pc;
>>>       target_ulong cs_base;
>>>       CPUArchState *env;
>>> -    tb_page_addr_t phys_page1;
>>> +    tb_page_addr_t page_addr0;
>> We don't actually document that this is an offset here (or indeed in
>> TranslationBlock) and the definition of tb_page_addr_t:
>>    /* Page tracking code uses ram addresses in system mode, and
>> virtual
>>       addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
>>       type.  */
>>    #if defined(CONFIG_USER_ONLY)
>>    typedef abi_ulong tb_page_addr_t;
>>    #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
>>    #else
>>    typedef ram_addr_t tb_page_addr_t;
>>    #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
>>    #endif
>> implies these are full size pointers into the guests address space.
>
> And that's what I've got.  What we we were storing in phys_page1
> before was a full size pointer that was page aligned.  I'm now
> dropping the page alignment and having a full size pointer to the
> exact first byte of the translated code.

OK then I'm confused by the commit message which says:

  Let tb->page_addr[0] contain the offset within the page of the
  start of the translation block

> Is that clearer?  How would you improve the wording?
>
>
> r~
>
>> Either we need a new type (tb_page_offset_t) or to properly comment the
>> structures with what they mean.
>> Otherwise:
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> 


-- 
Alex Bennée


  reply	other threads:[~2022-10-03 15:08 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-30 21:26 [PATCH v6 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Richard Henderson
2022-09-30 21:26 ` [PATCH v6 01/18] cpu: cache CPUClass in CPUState for hot code paths Richard Henderson
2022-09-30 21:26 ` [PATCH v6 02/18] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs Richard Henderson
2022-09-30 21:26 ` [PATCH v6 03/18] cputlb: used cached CPUClass in our hot-paths Richard Henderson
2022-09-30 21:26 ` [PATCH v6 04/18] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull Richard Henderson
2022-09-30 21:26 ` [PATCH v6 05/18] accel/tcg: Drop addr member from SavedIOTLB Richard Henderson
2022-09-30 21:26 ` [PATCH v6 06/18] accel/tcg: Suppress auto-invalidate in probe_access_internal Richard Henderson
2022-09-30 21:26 ` [PATCH v6 07/18] accel/tcg: Introduce probe_access_full Richard Henderson
2022-09-30 21:26 ` [PATCH v6 08/18] accel/tcg: Introduce tlb_set_page_full Richard Henderson
2022-09-30 21:26 ` [PATCH v6 09/18] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA Richard Henderson
2022-09-30 21:26 ` [PATCH v6 10/18] accel/tcg: Remove PageDesc code_bitmap Richard Henderson
2022-09-30 21:26 ` [PATCH v6 11/18] accel/tcg: Use bool for page_find_alloc Richard Henderson
2022-09-30 21:26 ` [PATCH v6 12/18] accel/tcg: Use DisasContextBase in plugin_gen_tb_start Richard Henderson
2022-09-30 21:26 ` [PATCH v6 13/18] accel/tcg: Do not align tb->page_addr[0] Richard Henderson
2022-10-03 12:47   ` Alex Bennée
2022-10-03 13:54     ` Richard Henderson
2022-10-03 14:59       ` Alex Bennée [this message]
2022-09-30 21:26 ` [PATCH v6 14/18] accel/tcg: Inline tb_flush_jmp_cache Richard Henderson
2022-10-03 12:51   ` Alex Bennée
2022-09-30 21:26 ` [PATCH v6 15/18] include/hw/core: Create struct CPUJumpCache Richard Henderson
2022-10-03 12:57   ` Alex Bennée
2022-09-30 21:26 ` [PATCH v6 16/18] hw/core: Add CPUClass.get_pc Richard Henderson
2022-09-30 21:56   ` Taylor Simpson
2022-10-03  7:58   ` Mark Cave-Ayland
2022-10-03 13:03   ` Alex Bennée
2022-09-30 21:26 ` [PATCH v6 17/18] accel/tcg: Introduce tb_pc and log_pc Richard Henderson
2022-09-30 21:26 ` [PATCH v6 18/18] accel/tcg: Introduce TARGET_TB_PCREL Richard Henderson
2022-10-03 13:46   ` Alex Bennée
2022-09-30 21:29 ` [PATCH v6 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Richard Henderson
2022-10-03 16:22 ` Alex Bennée

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