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Fri, 30 Sep 2022 15:55:55 +0000 (GMT) Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0A8AE5804E; Fri, 30 Sep 2022 15:55:55 +0000 (GMT) Received: from localhost (unknown [9.160.76.206]) by smtpav06.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Fri, 30 Sep 2022 15:55:54 +0000 (GMT) From: Fabiano Rosas To: Matheus Ferst , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: Re: [RFC PATCH v2 03/29] target/ppc: split interrupt masking and delivery from ppc_hw_interrupt In-Reply-To: <20220927201544.4088567-4-matheus.ferst@eldorado.org.br> References: <20220927201544.4088567-1-matheus.ferst@eldorado.org.br> <20220927201544.4088567-4-matheus.ferst@eldorado.org.br> Date: Fri, 30 Sep 2022 12:55:52 -0300 Message-ID: <87tu4o6elz.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 1ksFxukfUoUXt31w7iy_4KWj0RSzYZSA X-Proofpoint-ORIG-GUID: 7YdSnGakhYfQS8G-T5ZospvG5Unhuzbc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-30_04,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 clxscore=1015 spamscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209300099 Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Matheus Ferst writes: > Split ppc_hw_interrupt into an interrupt masking method, > ppc_next_unmasked_interrupt, and an interrupt processing method, > ppc_deliver_interrupt. > > @@ -1822,20 +1782,106 @@ static void ppc_hw_interrupt(CPUPPCState *env) > */ > if (FIELD_EX64(env->msr, MSR, PR) && > (env->spr[SPR_BESCR] & BESCR_GE)) { > - env->pending_interrupts &= ~PPC_INTERRUPT_EBB; > - > - if (env->spr[SPR_BESCR] & BESCR_PMEO) { > - powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); > - } else if (env->spr[SPR_BESCR] & BESCR_EEO) { > - powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB); > - } > - > - return; > + return PPC_INTERRUPT_EBB; > } > } > } > > - if (env->resume_as_sreset) { > + return 0; > +} > + > +static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt) > +{ > + PowerPCCPU *cpu = env_archcpu(env); > + CPUState *cs = env_cpu(env); > + > + switch (interrupt) { > + case PPC_INTERRUPT_RESET: /* External reset */ > + env->pending_interrupts &= ~PPC_INTERRUPT_RESET; > + powerpc_excp(cpu, POWERPC_EXCP_RESET); > + break; > + case PPC_INTERRUPT_MCK: /* Machine check exception */ > + env->pending_interrupts &= ~PPC_INTERRUPT_MCK; > + powerpc_excp(cpu, POWERPC_EXCP_MCHECK); > + break; > +#if 0 /* TODO */ > + case PPC_INTERRUPT_DEBUG: /* External debug exception */ > + env->pending_interrupts &= ~PPC_INTERRUPT_DEBUG; > + powerpc_excp(cpu, POWERPC_EXCP_DEBUG); > + break; > +#endif > + > + case PPC_INTERRUPT_HDECR: /* Hypervisor decrementer exception */ > + /* HDEC clears on delivery */ > + env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; > + powerpc_excp(cpu, POWERPC_EXCP_HDECR); > + break; > + case PPC_INTERRUPT_HVIRT: /* Hypervisor virtualization interrupt */ > + powerpc_excp(cpu, POWERPC_EXCP_HVIRT); > + break; > + > + case PPC_INTERRUPT_EXT: > + if (books_vhyp_promotes_external_to_hvirt(cpu)) { > + powerpc_excp(cpu, POWERPC_EXCP_HVIRT); > + } else { > + powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL); > + } > + break; > + case PPC_INTERRUPT_CEXT: /* External critical interrupt */ > + powerpc_excp(cpu, POWERPC_EXCP_CRITICAL); > + break; > + > + case PPC_INTERRUPT_WDT: /* Watchdog timer on embedded PowerPC */ > + env->pending_interrupts &= ~PPC_INTERRUPT_WDT; > + powerpc_excp(cpu, POWERPC_EXCP_WDT); > + break; > + case PPC_INTERRUPT_CDOORBELL: > + env->pending_interrupts &= ~PPC_INTERRUPT_CDOORBELL; > + powerpc_excp(cpu, POWERPC_EXCP_DOORCI); > + break; > + case PPC_INTERRUPT_FIT: /* Fixed interval timer on embedded PowerPC */ > + env->pending_interrupts &= ~PPC_INTERRUPT_FIT; > + powerpc_excp(cpu, POWERPC_EXCP_FIT); > + break; > + case PPC_INTERRUPT_PIT: /* Programmable interval timer on embedded PowerPC */ > + env->pending_interrupts &= ~PPC_INTERRUPT_PIT; > + powerpc_excp(cpu, POWERPC_EXCP_PIT); > + break; > + case PPC_INTERRUPT_DECR: /* Decrementer exception */ > + if (ppc_decr_clear_on_delivery(env)) { > + env->pending_interrupts &= ~PPC_INTERRUPT_DECR; > + } > + powerpc_excp(cpu, POWERPC_EXCP_DECR); > + break; > + case PPC_INTERRUPT_DOORBELL: > + env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; > + if (is_book3s_arch2x(env)) { > + powerpc_excp(cpu, POWERPC_EXCP_SDOOR); > + } else { > + powerpc_excp(cpu, POWERPC_EXCP_DOORI); > + } > + break; > + case PPC_INTERRUPT_HDOORBELL: > + env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; > + powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); > + break; > + case PPC_INTERRUPT_PERFM: > + env->pending_interrupts &= ~PPC_INTERRUPT_PERFM; > + powerpc_excp(cpu, POWERPC_EXCP_PERFM); > + break; > + case PPC_INTERRUPT_THERM: /* Thermal interrupt */ > + env->pending_interrupts &= ~PPC_INTERRUPT_THERM; > + powerpc_excp(cpu, POWERPC_EXCP_THERM); > + break; > + case PPC_INTERRUPT_EBB: /* EBB exception */ > + env->pending_interrupts &= ~PPC_INTERRUPT_EBB; > + if (env->spr[SPR_BESCR] & BESCR_PMEO) { > + powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); > + } else if (env->spr[SPR_BESCR] & BESCR_EEO) { > + powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB); > + } > + break; > + case 0: > /* > * This is a bug ! It means that has_work took us out of halt without > * anything to deliver while in a PM state that requires getting > @@ -1847,8 +1893,10 @@ static void ppc_hw_interrupt(CPUPPCState *env) > * It generally means a discrepancy between the wakeup conditions in the > * processor has_work implementation and the logic in this function. > */ > - cpu_abort(env_cpu(env), > - "Wakeup from PM state but interrupt Undelivered"); > + assert(env->resume_as_sreset != 0); This should be: assert(!env->resume_as_sreset); > + break; > + default: > + cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt); > } > } > > @@ -1884,15 +1932,22 @@ bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > { > PowerPCCPU *cpu = POWERPC_CPU(cs); > CPUPPCState *env = &cpu->env; > + int interrupt; > > - if (interrupt_request & CPU_INTERRUPT_HARD) { > - ppc_hw_interrupt(env); > - if (env->pending_interrupts == 0) { > - cs->interrupt_request &= ~CPU_INTERRUPT_HARD; > - } > - return true; > + if ((interrupt_request & CPU_INTERRUPT_HARD) == 0) { > + return false; > } > - return false; > + > + interrupt = ppc_next_unmasked_interrupt(env); > + if (interrupt == 0) { > + return false; > + } > + > + ppc_deliver_interrupt(env, interrupt); > + if (env->pending_interrupts == 0) { > + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); > + } > + return true; > } > > #endif /* !CONFIG_USER_ONLY */