From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87613C433EF for ; Sat, 9 Apr 2022 09:18:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239117AbiDIJUb (ORCPT ); Sat, 9 Apr 2022 05:20:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229964AbiDIJUa (ORCPT ); Sat, 9 Apr 2022 05:20:30 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82A1D228D33; Sat, 9 Apr 2022 02:18:24 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1EF9D60FAB; Sat, 9 Apr 2022 09:18:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 78324C385A4; Sat, 9 Apr 2022 09:18:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649495903; bh=HRj2ph9RMUyXwra0gXtHRn1nyHaJjzAtQD3t2s5KYJ0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=AHS5Jj7J6JDx8J1TVTuAyBMocSIXGTxG3hMYNwaYcz7XgHW0aOfpb1J6uZZnPw6EE eMjMh2QWm3AQT2ZP1HinG15KNNRnhYLFwY2cY0Lw6bS6tFmaeIjcOCBwPOdjFlgsh6 XinfNqMUwLeQMVurCiXv+4NGPDOPz9u3ISFVF9sI296ypa54cMQmooHlBbAK36H9Ow KpclSoF1fDsvFINd/axKZPLgMjchk/1iaD8WBV/EBsCyRFxDFYD7sPO1SMiQDt5Rwu AinW/0BmtLnDSrrlVLQnsWIZhdDrd+RRyX4Ju48G8YZMdqalhATuzwklfaYvDHyTZ/ yl9vNSw/5aovQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=billy-the-mountain.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nd7Ea-002xta-UC; Sat, 09 Apr 2022 10:18:21 +0100 Date: Sat, 09 Apr 2022 10:18:20 +0100 Message-ID: <87tub21uoz.wl-maz@kernel.org> From: Marc Zyngier To: Brad Larson Cc: Linux ARM , Arnd Bergmann , Linus Walleij , Bartosz Golaszewski , Mark Brown , Serge Semin , Adrian Hunter , Ulf Hansson , Olof Johansson , David Clear , "open list:GPIO SUBSYSTEM" , linux-spi , linux-mmc , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List Subject: Re: [PATCH 11/11] arm64: dts: Add Pensando Elba SoC support In-Reply-To: References: <20220406233648.21644-1-brad@pensando.io> <20220406233648.21644-12-brad@pensando.io> <9c08f621be28dba65e811bc9cdedc882@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: brad@pensando.io, linux-arm-kernel@lists.infradead.org, arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, dac2@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Sat, 09 Apr 2022 03:38:55 +0100, Brad Larson wrote: > > On Thu, Apr 7, 2022 at 12:57 AM Marc Zyngier wrote: > > > > > + gic: interrupt-controller@800000 { > > > + compatible = "arm,gic-v3"; > > > + #interrupt-cells = <3>; > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + ranges; > > > + interrupt-controller; > > > + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ > > > + <0x0 0xa00000 0x0 0x200000>; /* GICR */ > > > > You are still missing the GICV and GICH regions that are > > provided by the CPU. I already pointed that out in [1]. > > > > The Cortex-A72 TRM will tell you where to find them (at > > an offset from PERIPHBASE). > > Hi Marc, > > Got the addresses, neither region is used, and will be included in the > next submission. Not sure what you mean by these regions being unused here (the Linux kernel definitely makes use of them). Note that you'll also need to add GICC (which I forgot to mention above). M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 519DBC433F5 for ; Sat, 9 Apr 2022 09:19:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SwLyg/xxDnF1Ihhe5mbO7K1BN8pL/629aBVF8X++Pm4=; b=qcL4m/NT1YoAf2 Y9LGZG5PWbwM07NFPdSVLXcdaSC6AaYmml/wsSjsPCkHQE2+Wef3aioN0BCbu3FmA/txQxjcmMuTf IaT0x8Lcae0/lb2v9p9ycjOCgbjW+R1Sp9a/TlxCpFIvV5HrAn+FBWb7yVF/uyskmcEhRWFdPW7RL v/paPZzA8LP7oWOr5cSqvbWJ1Pfho9Af+4XB3ydhINeGCJfTa4bqtmd6DZ4jYmHEqqp9FGaoFpuuJ nn58W+ofIR3gN8VwGK4Me2iM+HhkKJtGEwTHV6ib6qncLdlkIQ7XyUWel6/eT5F9V/XDmJ7PGb4zu Jm9+2LkSAB8XEXO7pIjw==; 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Sat, 09 Apr 2022 10:18:21 +0100 Date: Sat, 09 Apr 2022 10:18:20 +0100 Message-ID: <87tub21uoz.wl-maz@kernel.org> From: Marc Zyngier To: Brad Larson Cc: Linux ARM , Arnd Bergmann , Linus Walleij , Bartosz Golaszewski , Mark Brown , Serge Semin , Adrian Hunter , Ulf Hansson , Olof Johansson , David Clear , "open list:GPIO SUBSYSTEM" , linux-spi , linux-mmc , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List Subject: Re: [PATCH 11/11] arm64: dts: Add Pensando Elba SoC support In-Reply-To: References: <20220406233648.21644-1-brad@pensando.io> <20220406233648.21644-12-brad@pensando.io> <9c08f621be28dba65e811bc9cdedc882@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: brad@pensando.io, linux-arm-kernel@lists.infradead.org, arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, dac2@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220409_021824_666338_081B9453 X-CRM114-Status: GOOD ( 21.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, 09 Apr 2022 03:38:55 +0100, Brad Larson wrote: > > On Thu, Apr 7, 2022 at 12:57 AM Marc Zyngier wrote: > > > > > + gic: interrupt-controller@800000 { > > > + compatible = "arm,gic-v3"; > > > + #interrupt-cells = <3>; > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + ranges; > > > + interrupt-controller; > > > + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ > > > + <0x0 0xa00000 0x0 0x200000>; /* GICR */ > > > > You are still missing the GICV and GICH regions that are > > provided by the CPU. I already pointed that out in [1]. > > > > The Cortex-A72 TRM will tell you where to find them (at > > an offset from PERIPHBASE). > > Hi Marc, > > Got the addresses, neither region is used, and will be included in the > next submission. Not sure what you mean by these regions being unused here (the Linux kernel definitely makes use of them). Note that you'll also need to add GICC (which I forgot to mention above). M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel