From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0C8CC432BE for ; Sun, 29 Aug 2021 10:10:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8865E60C3F for ; Sun, 29 Aug 2021 10:10:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235033AbhH2KLp (ORCPT ); Sun, 29 Aug 2021 06:11:45 -0400 Received: from mail.kernel.org ([198.145.29.99]:41690 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234835AbhH2KLn (ORCPT ); Sun, 29 Aug 2021 06:11:43 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id F24E660E94; Sun, 29 Aug 2021 10:10:51 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mKHm5-007qIz-Tb; Sun, 29 Aug 2021 11:10:50 +0100 Date: Sun, 29 Aug 2021 11:10:49 +0100 Message-ID: <87tuj8d0ie.wl-maz@kernel.org> From: Marc Zyngier To: Huacai Chen Cc: Huacai Chen , Thomas Gleixner , LKML , Xuefeng Li , Jiaxun Yang Subject: Re: [PATCH V3 08/10] irqchip: Add LoongArch CPU interrupt controller support In-Reply-To: References: <20210825061152.3396398-1-chenhuacai@loongson.cn> <20210825061152.3396398-9-chenhuacai@loongson.cn> <87pmu1q5ms.wl-maz@kernel.org> <87v93pddzu.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: chenhuacai@gmail.com, chenhuacai@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, lixuefeng@loongson.cn, jiaxun.yang@flygoat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 29 Aug 2021 10:37:48 +0100, Huacai Chen wrote: > > Are you saying that there is no way for the interrupt controller > > driver to figure out the hwirq number on its own? That would seem > > pretty odd (even the MIPS GIC has that). Worse case, you can provide > > an arch-specific helper that exposes the current hwirq based on the > > vector that triggered. > We can get the hwirq number by reading CSR.ESTAT register, but in this > way "vectored interrupts" is meaningless. Let's face it, the way you use vectored interrupts makes zero sense already. The whole point of vectored interrupts is that the CPU can branch to the handler directly, making the interrupt handling cheaper as there should be no additional decoding and you can run the final handler immediately. Here, all your interrupts point to the same "default handler"... What do vectored interrupts bring? "Absolutely Nothing! (say it again!)" M. -- Without deviation from the norm, progress is not possible.