* [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode
@ 2018-10-04 18:29 Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 2/6] drm/i915/icl: Implement Display WA_1405510057 Radhakrishna Sripada
` (7 more replies)
0 siblings, 8 replies; 16+ messages in thread
From: Radhakrishna Sripada @ 2018-10-04 18:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
Gen11 Display suports 32 planes in total. Enable the new format in context
status to be used and expanded to 32 planes.
V2: Move the WA to display WA's(Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a71c507cfb9b..4fb8e9eef312 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2573,6 +2573,7 @@ enum i915_power_well_id {
/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
+#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
/* WaClearTdlStateAckDirtyBits */
#define GEN8_STATE_ACK _MMIO(0x20F0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1392aa56a55a..d4a464246760 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8734,6 +8734,10 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
/* This is not an Wa. Enable to reduce Sampler power */
I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
+
+ /* WaEnable32PlaneMode:icl */
+ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
+ _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
}
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.9.3
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 2/6] drm/i915/icl: Implement Display WA_1405510057
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
@ 2018-10-04 18:29 ` Radhakrishna Sripada
2018-10-17 21:49 ` Srivatsa, Anusha
2018-10-04 18:29 ` [PATCH v2 3/6] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Radhakrishna Sripada
` (6 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Radhakrishna Sripada @ 2018-10-04 18:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Paulo Zanoni
Display WA_1405510057 asks to not enable YUV 420 HDMI
10bpc when horizontal blank size mod 8 reminder is 2.
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 454f570275e9..fa6b39420e69 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1592,6 +1592,8 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
struct drm_atomic_state *state = crtc_state->base.state;
struct drm_connector_state *connector_state;
struct drm_connector *connector;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
int i;
if (HAS_GMCH_DISPLAY(dev_priv))
@@ -1640,7 +1642,13 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
/* Display WA #1139: glk */
if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
- crtc_state->base.adjusted_mode.htotal > 5460)
+ adjusted_mode->htotal > 5460)
+ return false;
+
+ /* Display Wa_1405510057:icl */
+ if (crtc_state->ycbcr420 && bpc == 10 && IS_ICELAKE(dev_priv) &&
+ (adjusted_mode->crtc_hblank_end -
+ adjusted_mode->crtc_hblank_start) % 8 == 2)
return false;
return true;
--
2.9.3
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 3/6] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 2/6] drm/i915/icl: Implement Display WA_1405510057 Radhakrishna Sripada
@ 2018-10-04 18:29 ` Radhakrishna Sripada
2018-10-12 19:01 ` Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 4/6] drm/i915/icl: WaAllowUMDToModifySamplerMode Radhakrishna Sripada
` (5 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Radhakrishna Sripada @ 2018-10-04 18:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
From: Oscar Mateo <oscar.mateo@intel.com>
Required to dinamically set 'Trilinear Filter Quality Mode'
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 4bcdeaf8d98f..69e247409050 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1009,6 +1009,8 @@ static void cnl_whitelist_build(struct whitelist *w)
static void icl_whitelist_build(struct whitelist *w)
{
+ /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+ whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
2.9.3
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 4/6] drm/i915/icl: WaAllowUMDToModifySamplerMode
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 2/6] drm/i915/icl: Implement Display WA_1405510057 Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 3/6] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Radhakrishna Sripada
@ 2018-10-04 18:29 ` Radhakrishna Sripada
2018-10-12 18:58 ` Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
` (4 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Radhakrishna Sripada @ 2018-10-04 18:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
From: Oscar Mateo <oscar.mateo@intel.com>
Required for Bindless samplers.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4fb8e9eef312..c8a187d8db0f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8632,6 +8632,8 @@ enum {
#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 69e247409050..65cd36cd2957 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1011,6 +1011,9 @@ static void icl_whitelist_build(struct whitelist *w)
{
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+ /* WaAllowUMDToModifySamplerMode:icl */
+ whitelist_reg(w, GEN10_SAMPLER_MODE);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
2.9.3
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (2 preceding siblings ...)
2018-10-04 18:29 ` [PATCH v2 4/6] drm/i915/icl: WaAllowUMDToModifySamplerMode Radhakrishna Sripada
@ 2018-10-04 18:29 ` Radhakrishna Sripada
2018-10-08 13:55 ` Mika Kuoppala
2018-10-09 7:18 ` Mika Kuoppala
2018-10-04 18:29 ` [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166 Radhakrishna Sripada
` (3 subsequent siblings)
7 siblings, 2 replies; 16+ messages in thread
From: Radhakrishna Sripada @ 2018-10-04 18:29 UTC (permalink / raw)
To: intel-gfx
Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
formats. Enabling fault handling could result in hangs with faults.
Disabling demand prefetch would disable binding table prefetch.
V2: Fix the stepping rivision to B0(Mika)
References: HSDES#1406609255, HSDES#1406573985
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8a187d8db0f..fa020425754f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7413,6 +7413,9 @@ enum {
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
+#define GEN7_SARCHKMD _MMIO(0xB000)
+#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
+
#define GEN7_L3SQCREG1 _MMIO(0xB010)
#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 65cd36cd2957..cf4f4c1f86ab 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -905,6 +905,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(GAMT_CHKN_BIT_REG,
I915_READ(GAMT_CHKN_BIT_REG) |
GAMT_CHKN_DISABLE_L3_COH_PIPE);
+
+ /* Wa_1406609255:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+ I915_WRITE(GEN7_SARCHKMD,
+ I915_READ(GEN7_SARCHKMD) |
+ GEN7_DISABLE_DEMAND_PREFETCH);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
2.9.3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (3 preceding siblings ...)
2018-10-04 18:29 ` [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
@ 2018-10-04 18:29 ` Radhakrishna Sripada
2018-10-08 14:02 ` Mika Kuoppala
2018-10-09 7:19 ` Mika Kuoppala
2018-10-04 19:08 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/icl: Add WaEnable32PlaneMode Patchwork
` (2 subsequent siblings)
7 siblings, 2 replies; 16+ messages in thread
From: Radhakrishna Sripada @ 2018-10-04 18:29 UTC (permalink / raw)
To: intel-gfx
From: Anuj Phogat <anuj.phogat@gmail.com>
Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
Disable the Sampler state prefetch functionality in the SARB by
programming 0xB000[30] to '1'. This is to be done at boot time
and the feature must remain disabled permanently.
Fixes flaky tex-mip-level-selection* piglit tests with Mesa i965
driver.
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa020425754f..0c544161ed47 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7415,6 +7415,7 @@ enum {
#define GEN7_SARCHKMD _MMIO(0xB000)
#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
+#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
#define GEN7_L3SQCREG1 _MMIO(0xB010)
#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index cf4f4c1f86ab..7157115e5bc9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -910,7 +910,8 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
I915_WRITE(GEN7_SARCHKMD,
I915_READ(GEN7_SARCHKMD) |
- GEN7_DISABLE_DEMAND_PREFETCH);
+ GEN7_DISABLE_DEMAND_PREFETCH |
+ GEN7_DISABLE_SAMPLER_PREFETCH);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
2.9.3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/icl: Add WaEnable32PlaneMode
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (4 preceding siblings ...)
2018-10-04 18:29 ` [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166 Radhakrishna Sripada
@ 2018-10-04 19:08 ` Patchwork
2018-10-05 2:32 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-17 22:13 ` [PATCH v2 1/6] " Srivatsa, Anusha
7 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2018-10-04 19:08 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/icl: Add WaEnable32PlaneMode
URL : https://patchwork.freedesktop.org/series/50569/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4932 -> Patchwork_10364 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/50569/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10364 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_evict:
fi-bsw-kefka: PASS -> DMESG-WARN (fdo#107709)
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: PASS -> FAIL (fdo#103167)
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#107709 https://bugs.freedesktop.org/show_bug.cgi?id=107709
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
== Participating hosts (48 -> 41) ==
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-gdg-551
== Build changes ==
* Linux: CI_DRM_4932 -> Patchwork_10364
CI_DRM_4932: 21f90148bf7adb33d82580013a5697a6bbb88248 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4669: 5f40e617cd9c1e089f4a2d79c53a417d891e3e3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10364: 0e5bcb1216ffcd65716a0840a879a269e4866bbb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0e5bcb1216ff drm/i915/icl:Add Wa_1606682166
fd1a33cc069b drm/i915/icl: Add Wa_1406609255
a593fe319225 drm/i915/icl: WaAllowUMDToModifySamplerMode
bfdffb94fd07 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
914ba5ff7ca8 drm/i915/icl: Implement Display WA_1405510057
2f27b6f17cd5 drm/i915/icl: Add WaEnable32PlaneMode
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10364/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [v2,1/6] drm/i915/icl: Add WaEnable32PlaneMode
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (5 preceding siblings ...)
2018-10-04 19:08 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/icl: Add WaEnable32PlaneMode Patchwork
@ 2018-10-05 2:32 ` Patchwork
2018-10-17 22:13 ` [PATCH v2 1/6] " Srivatsa, Anusha
7 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2018-10-05 2:32 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/icl: Add WaEnable32PlaneMode
URL : https://patchwork.freedesktop.org/series/50569/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4932_full -> Patchwork_10364_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10364_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_schedule@pi-ringfull-bsd:
shard-skl: NOTRUN -> FAIL (fdo#103158)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1
igt@kms_color@pipe-b-degamma:
shard-apl: PASS -> FAIL (fdo#104782)
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-glk: PASS -> FAIL (fdo#103232) +2
shard-apl: PASS -> FAIL (fdo#103191, fdo#103232) +1
igt@kms_cursor_crc@cursor-128x42-random:
shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359)
igt@kms_cursor_crc@cursor-256x256-random:
shard-apl: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_legacy@cursor-vs-flip-atomic:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763)
igt@kms_cursor_legacy@flip-vs-cursor-legacy:
shard-skl: PASS -> FAIL (fdo#102670)
igt@kms_fbcon_fbt@psr:
shard-skl: NOTRUN -> FAIL (fdo#107882)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: PASS -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-apl: PASS -> FAIL (fdo#103167) +6
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
shard-glk: PASS -> FAIL (fdo#103167) +4
{igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb}:
shard-skl: NOTRUN -> FAIL (fdo#108145) +2
igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
shard-glk: PASS -> FAIL (fdo#103166) +1
shard-apl: PASS -> FAIL (fdo#103166) +2
igt@kms_setmode@basic:
shard-hsw: PASS -> FAIL (fdo#99912)
igt@perf@polling:
shard-hsw: PASS -> FAIL (fdo#102252)
==== Possible fixes ====
igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
shard-glk: FAIL (fdo#108145) -> PASS
igt@kms_color@pipe-a-ctm-max:
shard-apl: FAIL (fdo#108147) -> PASS
igt@kms_cursor_crc@cursor-256x256-onscreen:
shard-glk: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-64x21-sliding:
shard-apl: FAIL (fdo#103232) -> PASS +2
igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS
igt@kms_draw_crc@draw-method-xrgb8888-render-untiled:
shard-skl: FAIL -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
shard-apl: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
shard-glk: FAIL (fdo#103167) -> PASS +1
igt@kms_plane@plane-position-covered-pipe-b-planes:
shard-glk: FAIL (fdo#103166) -> PASS
igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
shard-apl: FAIL (fdo#103166) -> PASS
igt@pm_rpm@modeset-lpsp-stress-no-wait:
shard-skl: INCOMPLETE (fdo#107807) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4932 -> Patchwork_10364
CI_DRM_4932: 21f90148bf7adb33d82580013a5697a6bbb88248 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4669: 5f40e617cd9c1e089f4a2d79c53a417d891e3e3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10364: 0e5bcb1216ffcd65716a0840a879a269e4866bbb @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10364/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255
2018-10-04 18:29 ` [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
@ 2018-10-08 13:55 ` Mika Kuoppala
2018-10-09 7:18 ` Mika Kuoppala
1 sibling, 0 replies; 16+ messages in thread
From: Mika Kuoppala @ 2018-10-08 13:55 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx
Radhakrishna Sripada <radhakrishna.sripada@intel.com> writes:
> Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
> formats. Enabling fault handling could result in hangs with faults.
> Disabling demand prefetch would disable binding table prefetch.
>
> V2: Fix the stepping rivision to B0(Mika)
>
> References: HSDES#1406609255, HSDES#1406573985
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c8a187d8db0f..fa020425754f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7413,6 +7413,9 @@ enum {
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> +#define GEN7_SARCHKMD _MMIO(0xB000)
> +#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
> +
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 65cd36cd2957..cf4f4c1f86ab 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -905,6 +905,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> I915_WRITE(GAMT_CHKN_BIT_REG,
> I915_READ(GAMT_CHKN_BIT_REG) |
> GAMT_CHKN_DISABLE_L3_COH_PIPE);
> +
> + /* Wa_1406609255:icl (pre-prod) */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> + I915_WRITE(GEN7_SARCHKMD,
> + I915_READ(GEN7_SARCHKMD) |
> + GEN7_DISABLE_DEMAND_PREFETCH);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 2.9.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166
2018-10-04 18:29 ` [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166 Radhakrishna Sripada
@ 2018-10-08 14:02 ` Mika Kuoppala
2018-10-09 7:19 ` Mika Kuoppala
1 sibling, 0 replies; 16+ messages in thread
From: Mika Kuoppala @ 2018-10-08 14:02 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx
Radhakrishna Sripada <radhakrishna.sripada@intel.com> writes:
> From: Anuj Phogat <anuj.phogat@gmail.com>
>
> Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
> Disable the Sampler state prefetch functionality in the SARB by
> programming 0xB000[30] to '1'. This is to be done at boot time
> and the feature must remain disabled permanently.
>
> Fixes flaky tex-mip-level-selection* piglit tests with Mesa i965
> driver.
>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_workarounds.c | 3 ++-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa020425754f..0c544161ed47 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7415,6 +7415,7 @@ enum {
>
> #define GEN7_SARCHKMD _MMIO(0xB000)
> #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
> +#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
>
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index cf4f4c1f86ab..7157115e5bc9 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -910,7 +910,8 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> I915_WRITE(GEN7_SARCHKMD,
> I915_READ(GEN7_SARCHKMD) |
> - GEN7_DISABLE_DEMAND_PREFETCH);
> + GEN7_DISABLE_DEMAND_PREFETCH |
> + GEN7_DISABLE_SAMPLER_PREFETCH);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 2.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255
2018-10-04 18:29 ` [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
2018-10-08 13:55 ` Mika Kuoppala
@ 2018-10-09 7:18 ` Mika Kuoppala
1 sibling, 0 replies; 16+ messages in thread
From: Mika Kuoppala @ 2018-10-09 7:18 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx
Radhakrishna Sripada <radhakrishna.sripada@intel.com> writes:
> Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
> formats. Enabling fault handling could result in hangs with faults.
> Disabling demand prefetch would disable binding table prefetch.
>
> V2: Fix the stepping rivision to B0(Mika)
>
> References: HSDES#1406609255, HSDES#1406573985
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Pushed, thanks for the patch.
-Mika
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c8a187d8db0f..fa020425754f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7413,6 +7413,9 @@ enum {
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> +#define GEN7_SARCHKMD _MMIO(0xB000)
> +#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
> +
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 65cd36cd2957..cf4f4c1f86ab 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -905,6 +905,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> I915_WRITE(GAMT_CHKN_BIT_REG,
> I915_READ(GAMT_CHKN_BIT_REG) |
> GAMT_CHKN_DISABLE_L3_COH_PIPE);
> +
> + /* Wa_1406609255:icl (pre-prod) */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> + I915_WRITE(GEN7_SARCHKMD,
> + I915_READ(GEN7_SARCHKMD) |
> + GEN7_DISABLE_DEMAND_PREFETCH);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 2.9.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166
2018-10-04 18:29 ` [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166 Radhakrishna Sripada
2018-10-08 14:02 ` Mika Kuoppala
@ 2018-10-09 7:19 ` Mika Kuoppala
1 sibling, 0 replies; 16+ messages in thread
From: Mika Kuoppala @ 2018-10-09 7:19 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx
Radhakrishna Sripada <radhakrishna.sripada@intel.com> writes:
> From: Anuj Phogat <anuj.phogat@gmail.com>
>
> Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
> Disable the Sampler state prefetch functionality in the SARB by
> programming 0xB000[30] to '1'. This is to be done at boot time
> and the feature must remain disabled permanently.
>
> Fixes flaky tex-mip-level-selection* piglit tests with Mesa i965
> driver.
>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Pushed to dinq, thanks for the patch.
-Mika
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_workarounds.c | 3 ++-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa020425754f..0c544161ed47 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7415,6 +7415,7 @@ enum {
>
> #define GEN7_SARCHKMD _MMIO(0xB000)
> #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
> +#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
>
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index cf4f4c1f86ab..7157115e5bc9 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -910,7 +910,8 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> I915_WRITE(GEN7_SARCHKMD,
> I915_READ(GEN7_SARCHKMD) |
> - GEN7_DISABLE_DEMAND_PREFETCH);
> + GEN7_DISABLE_DEMAND_PREFETCH |
> + GEN7_DISABLE_SAMPLER_PREFETCH);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 2.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 4/6] drm/i915/icl: WaAllowUMDToModifySamplerMode
2018-10-04 18:29 ` [PATCH v2 4/6] drm/i915/icl: WaAllowUMDToModifySamplerMode Radhakrishna Sripada
@ 2018-10-12 18:58 ` Radhakrishna Sripada
0 siblings, 0 replies; 16+ messages in thread
From: Radhakrishna Sripada @ 2018-10-12 18:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
On Thu, Oct 04, 2018 at 11:29:37AM -0700, Radhakrishna Sripada wrote:
> From: Oscar Mateo <oscar.mateo@intel.com>
>
> Required for Bindless samplers.
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4fb8e9eef312..c8a187d8db0f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8632,6 +8632,8 @@ enum {
> #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
> #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
>
> +#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
> +
> /* IVYBRIDGE DPF */
> #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
> #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 69e247409050..65cd36cd2957 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1011,6 +1011,9 @@ static void icl_whitelist_build(struct whitelist *w)
> {
> /* WaAllowUMDToModifyHalfSliceChicken7:icl */
> whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
> +
> + /* WaAllowUMDToModifySamplerMode:icl */
> + whitelist_reg(w, GEN10_SAMPLER_MODE);
User space consumer mesa: https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_state_upload.c#L72
Regards,
Radhakrishna(RK) Sripada
> }
>
> static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> --
> 2.9.3
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/6] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
2018-10-04 18:29 ` [PATCH v2 3/6] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Radhakrishna Sripada
@ 2018-10-12 19:01 ` Radhakrishna Sripada
0 siblings, 0 replies; 16+ messages in thread
From: Radhakrishna Sripada @ 2018-10-12 19:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
On Thu, Oct 04, 2018 at 11:29:36AM -0700, Radhakrishna Sripada wrote:
> From: Oscar Mateo <oscar.mateo@intel.com>
>
> Required to dinamically set 'Trilinear Filter Quality Mode'
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 4bcdeaf8d98f..69e247409050 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1009,6 +1009,8 @@ static void cnl_whitelist_build(struct whitelist *w)
>
> static void icl_whitelist_build(struct whitelist *w)
> {
> + /* WaAllowUMDToModifyHalfSliceChicken7:icl */
> + whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
Userspace consumer mesa: https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/intel/vulkan/genX_state.c#L196
Regards,
Radhakrishna(RK) Sripada
> }
>
> static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> --
> 2.9.3
>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/6] drm/i915/icl: Implement Display WA_1405510057
2018-10-04 18:29 ` [PATCH v2 2/6] drm/i915/icl: Implement Display WA_1405510057 Radhakrishna Sripada
@ 2018-10-17 21:49 ` Srivatsa, Anusha
0 siblings, 0 replies; 16+ messages in thread
From: Srivatsa, Anusha @ 2018-10-17 21:49 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx; +Cc: Zanoni, Paulo R, Vivi, Rodrigo
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Radhakrishna Sripada
>Sent: Thursday, October 4, 2018 11:30 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Zanoni, Paulo R
><paulo.r.zanoni@intel.com>
>Subject: [Intel-gfx] [PATCH v2 2/6] drm/i915/icl: Implement Display
>WA_1405510057
>
>Display WA_1405510057 asks to not enable YUV 420 HDMI 10bpc when
>horizontal blank size mod 8 reminder is 2.
>
>Cc: James Ausmus <james.ausmus@intel.com>
>Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/intel_hdmi.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
>b/drivers/gpu/drm/i915/intel_hdmi.c
>index 454f570275e9..fa6b39420e69 100644
>--- a/drivers/gpu/drm/i915/intel_hdmi.c
>+++ b/drivers/gpu/drm/i915/intel_hdmi.c
>@@ -1592,6 +1592,8 @@ static bool hdmi_deep_color_possible(const struct
>intel_crtc_state *crtc_state,
> struct drm_atomic_state *state = crtc_state->base.state;
> struct drm_connector_state *connector_state;
> struct drm_connector *connector;
>+ const struct drm_display_mode *adjusted_mode =
>+ &crtc_state->base.adjusted_mode;
> int i;
>
> if (HAS_GMCH_DISPLAY(dev_priv))
>@@ -1640,7 +1642,13 @@ static bool hdmi_deep_color_possible(const struct
>intel_crtc_state *crtc_state,
>
> /* Display WA #1139: glk */
> if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
>- crtc_state->base.adjusted_mode.htotal > 5460)
>+ adjusted_mode->htotal > 5460)
>+ return false;
>+
>+ /* Display Wa_1405510057:icl */
>+ if (crtc_state->ycbcr420 && bpc == 10 && IS_ICELAKE(dev_priv) &&
>+ (adjusted_mode->crtc_hblank_end -
>+ adjusted_mode->crtc_hblank_start) % 8 == 2)
> return false;
>
> return true;
>--
>2.9.3
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
` (6 preceding siblings ...)
2018-10-05 2:32 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-10-17 22:13 ` Srivatsa, Anusha
7 siblings, 0 replies; 16+ messages in thread
From: Srivatsa, Anusha @ 2018-10-17 22:13 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx; +Cc: Thierry, Michel
>-----Original Message-----
>From: Sripada, Radhakrishna
>Sent: Thursday, October 4, 2018 11:30 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Chris Wilson
><chris@chris-wilson.co.uk>; Thierry, Michel <michel.thierry@intel.com>; Ausmus,
>James <james.ausmus@intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>
>Subject: [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode
>
>Gen11 Display suports 32 planes in total. Enable the new format in context status
>to be used and expanded to 32 planes.
>
>V2: Move the WA to display WA's(Chris)
>
>Cc: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Michel Thierry <michel.thierry@intel.com>
>Cc: James Ausmus <james.ausmus@intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index a71c507cfb9b..4fb8e9eef312 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2573,6 +2573,7 @@ enum i915_power_well_id {
> /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ #define
>GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
> #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
>+#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
>
> /* WaClearTdlStateAckDirtyBits */
> #define GEN8_STATE_ACK _MMIO(0x20F0)
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index 1392aa56a55a..d4a464246760 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -8734,6 +8734,10 @@ static void icl_init_clock_gating(struct
>drm_i915_private *dev_priv)
> /* This is not an Wa. Enable to reduce Sampler power */
> I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) &
>~DFR_DISABLE);
>+
>+ /* WaEnable32PlaneMode:icl */
>+ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
>+ _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
> }
>
> static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>--
>2.9.3
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^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2018-10-17 22:13 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 2/6] drm/i915/icl: Implement Display WA_1405510057 Radhakrishna Sripada
2018-10-17 21:49 ` Srivatsa, Anusha
2018-10-04 18:29 ` [PATCH v2 3/6] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Radhakrishna Sripada
2018-10-12 19:01 ` Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 4/6] drm/i915/icl: WaAllowUMDToModifySamplerMode Radhakrishna Sripada
2018-10-12 18:58 ` Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
2018-10-08 13:55 ` Mika Kuoppala
2018-10-09 7:18 ` Mika Kuoppala
2018-10-04 18:29 ` [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166 Radhakrishna Sripada
2018-10-08 14:02 ` Mika Kuoppala
2018-10-09 7:19 ` Mika Kuoppala
2018-10-04 19:08 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/icl: Add WaEnable32PlaneMode Patchwork
2018-10-05 2:32 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-17 22:13 ` [PATCH v2 1/6] " Srivatsa, Anusha
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