* [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers
@ 2022-06-27 11:39 Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 01/13] APCI: irq: Add support for multiple GSI domains Jianmin Lv
` (12 more replies)
0 siblings, 13 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
boot protocol LoongArch-specific interrupt controllers (similar to APIC)
are already added in the ACPI Specification 6.5(which may be published in
early June this year and the board is reviewing the draft).
Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
work together with LS7A chipsets. The irq chips in LoongArch computers
include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are
per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are all
controllers out of CPU (i.e., in chipsets). These controllers (in other
words, irqchips) are linked in a hierarchy, and there are two models of
hierarchy (legacy model and extended model).
Legacy IRQ model:
In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC.
+---------------------------------------------+
| |
| +-----+ +---------+ +-------+ |
| | IPI | --> | CPUINTC | <-- | Timer | |
| +-----+ +---------+ +-------+ |
| ^ |
| | |
| +---------+ +-------+ |
| | LIOINTC | <-- | UARTs | |
| +---------+ +-------+ |
| ^ |
| | |
| +-----------+ |
| | HTVECINTC | |
| +-----------+ |
| ^ ^ |
| | | |
| +---------+ +---------+ |
| | PCH-PIC | | PCH-MSI | |
| +---------+ +---------+ |
| ^ ^ ^ |
| | | | |
| +---------+ +---------+ +---------+ |
| | PCH-LPC | | Devices | | Devices | |
| +---------+ +---------+ +---------+ |
| ^ |
| | |
| +---------+ |
| | Devices | |
| +---------+ |
| |
| |
+---------------------------------------------+
Extended IRQ model:
In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
gathered by EIOINTC, and then go to to CPUINTC directly.
+--------------------------------------------------------+
| |
| +-----+ +---------+ +-------+ |
| | IPI | --> | CPUINTC | <-- | Timer | |
| +-----+ +---------+ +-------+ |
| ^ ^ |
| | | |
| +---------+ +---------+ +-------+ |
| | EIOINTC | | LIOINTC | <-- | UARTs | |
| +---------+ +---------+ +-------+ |
| ^ ^ |
| | | |
| +---------+ +---------+ |
| | PCH-PIC | | PCH-MSI | |
| +---------+ +---------+ |
| ^ ^ ^ |
| | | | |
| +---------+ +---------+ +---------+ |
| | PCH-LPC | | Devices | | Devices | |
| +---------+ +---------+ +---------+ |
| ^ |
| | |
| +---------+ |
| | Devices | |
| +---------+ |
| |
| |
+--------------------------------------------------------+
The hierarchy model is constructed by parsing irq contronler structures
in MADT. Some controllers((e.g. LIOINTC, HTVECINTC, EIOINTC and PCH-LPC)
are hardcodingly connected to their parents, so their irqdomins are
separately routed to their parents in a fixed way. Some controllers
(e.g. PCH-PIC and PCH-MSI) could be routed to different parents for different
CPU. The firmware will config EIOINTC for the newer CPU and config HTVECINTC
for old CPU in MADT. By this way, PCH-PIC and PCH-MSI irqdomain can only be
routed one parent irqdomin: HTVECINTC or EIOINTC.
Example of irqchip topology in a system with two chipsets:
+------------------------------------------------------------+
| |
| +------------------+ |
| | CPUINTC | |
| +------------------+ |
| ^ ^ |
| | | |
| +----------+ +----------+ |
| | EIOINTC 0| | EIOINTC 1| |
| +----------+ +----------+ |
| ^ ^ ^ ^ |
| | | | | |
| +----------+ +----------+ +----------+ +----------+ |
| | PCH-PIC 0| | PCH-MSI 0| | PCH-PIC 1| | PCH-MSI 1| |
| +----------+ +----------+ +----------+ +----------+ |
| |
| |
+------------------------------------------------------------+
For systems with two chipsets, there are tow group(consists of EIOINTC, PCH-PIC and PCH-MSI) irqdomains,
and each group has same node id. So we defined a structure to mantain the relation of node and it's parent irqdomain.
struct acpi_vector_group {
int node;
int pci_segment;
struct irq_domain *parent;
};
The initialization and use of acpi_vector_group array are following:
1 Entry of struct acpi_vector_group array initialization:
By parsing MCFG, the node id（from bit44-47 of Base Address）and pci segment are extracted. And from MADT, we have the node id of each EIOINTC.
entry.node = node id of pci segment
entry.pci_segment = pci segment (only for msi irqdomain)
By matching node id of entry and EIOINTC to set parent.
entry.parent = EIOINTC irqdomain(node id of EIOINTC == node id of pci segment)
2 Get parent irqdomain for PCH-PIC:
From MADT, we have the node id of each PCH-PIC(from bit44-47 of Base Address).
if (node of entry i == node of PCH-PIC)
return entrys[i].parent;
3 Get parent irqdomain for PCH-MSI of pci segment:
return entrys[i].parent; (i is the index of msi irqdomain)
4 How to select a correct irqdomain to map irq for a device?
For devices using legacy irq behind PCH-PIC, GSI is used to select correct PCH-PIC irqdomain.
For devices using msi irq behind PCH-MSI, the pci segmen of the device is used to select correct PCH-MSI irqdomain.
V1 -> V2:
1, Remove queued patches;
2, Move common logic of DT/ACPI probing to common functions;
3, Split .suspend()/.resume() functions to separate patches.
V2 -> V3:
1, Fix a bug for loongson-pch-pic probe;
2, Some minor improvements for LPC controller.
V3 -> V4:
1, Rework the CPU interrupt controller driver;
2, Some minor improvements for other controllers.
V4 -> V5:
1, Add a description of LoonArch's IRQ model;
2, Support multiple EIOINTCs in one system;
3, Some minor improvements for other controllers.
V5 -> V6:
1, Attach a fwnode to CPUINTC irq domain;
2, Use raw spinlock instead of generic spinlock;
3, Improve the method of restoring EIOINTC state;
4, Update documentation, comments and commit messages.
V6 -> V7:
1, Fix build warnings reported by kernel test robot.
V7 -> V8:
1, Add arguments sanity checking for irqchip init functions;
2, Support Loongson-3C5000 (One NUMA Node includes 4 EIOINTC Node).
V8 -> V9:
1, Rebase on 5.17-rc5;
2, Update cover letter;
3, Some small improvements.
V9 -> V10:
1, Rebase on 5.17-rc6;
2, Fix build warnings reported by kernel test robot.
V10 -> V11:
1, Rebase on 5.18-rc4;
2, Fix irq affinity setting for EIOINTC;
3, Fix hwirq allocation failure for EIOINTC.
V11 -> RFC:
1, Refactored the way to build irqchip hierarchy topology.
RFC -> RFC V2:
1, Move all IO-interrupt related code to driver/irqchip from arch directory.
2. Add description for an example of two chipsets system.
RFC V2 -> RFC V3:
1, Add support for multiple GSI domains
2, Use ACPI_GENERIC_GSI for GSI handling
3, Drop suspend-resume stuff
4, Export fwnode handles instead of irq domain handles
RFC V3 -> V12:
1, Address patch attributions of the patch series
V12 -> V13
1 Based on 5.19-rc2
2 Remove arch specified gsi code
3 Split some 'common' code into the various drivers where they belong.
4 Allow acpi_gsi_to_irq() to have an arch-specific fallback
Huacai Chen (7):
irqchip: Add Loongson PCH LPC controller support
irqchip/loongson-pch-pic: Add ACPI init support
irqchip/loongson-pch-msi: Add ACPI init support
irqchip/loongson-htvec: Add ACPI init support
irqchip/loongson-liointc: Add ACPI init support
irqchip: Add Loongson Extended I/O interrupt controller support
irqchip: Add LoongArch CPU interrupt controller support
Jianmin Lv (4):
genirq/generic_chip: export irq_unmap_generic_chip
LoongArch: Use ACPI_GENERIC_GSI for gsi handling
irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
LoongArch: Fix irq number for timer and ipi
Marc Zyngier (2):
APCI: irq: Add support for multiple GSI domains
ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
arch/loongarch/Kconfig | 1 +
arch/loongarch/include/asm/irq.h | 43 ++--
arch/loongarch/kernel/acpi.c | 65 ------
arch/loongarch/kernel/irq.c | 37 +++-
arch/loongarch/kernel/time.c | 2 +-
drivers/acpi/bus.c | 3 +
drivers/acpi/irq.c | 58 +++--
drivers/irqchip/Kconfig | 28 +++
drivers/irqchip/Makefile | 3 +
drivers/irqchip/irq-gic-v3.c | 18 +-
drivers/irqchip/irq-gic.c | 18 +-
drivers/irqchip/irq-loongarch-cpu.c | 168 +++++++++++++++
drivers/irqchip/irq-loongson-eiointc.c | 375 +++++++++++++++++++++++++++++++++
drivers/irqchip/irq-loongson-htvec.c | 121 ++++++++---
drivers/irqchip/irq-loongson-liointc.c | 227 +++++++++++++-------
drivers/irqchip/irq-loongson-pch-lpc.c | 203 ++++++++++++++++++
drivers/irqchip/irq-loongson-pch-msi.c | 147 +++++++++----
drivers/irqchip/irq-loongson-pch-pic.c | 200 +++++++++++++++---
include/linux/acpi.h | 4 +-
include/linux/cpuhotplug.h | 1 +
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 2 +-
22 files changed, 1416 insertions(+), 309 deletions(-)
create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c
--
1.8.3.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH V13 01/13] APCI: irq: Add support for multiple GSI domains
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-28 12:50 ` Hanjun Guo
2022-06-27 11:39 ` [PATCH V13 02/13] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
` (11 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
From: Marc Zyngier <maz@kernel.org>
In an unfortunate departure from the ACPI spec, the LoongArch
architecture split its GSI space across multiple interrupt
controllers.
In order to be able to reuse sthe core code and prevent
architectures from reinventing an already square wheel, offer
the arch code the ability to register a dispatcher function
that will return the domain fwnode for a given GSI.
The ARM GIC drivers are updated to support this (with a single
domain, as intended).
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/acpi/irq.c | 40 +++++++++++++++++++++++++---------------
drivers/irqchip/irq-gic-v3.c | 18 ++++++++++++------
drivers/irqchip/irq-gic.c | 18 ++++++++++++------
include/linux/acpi.h | 2 +-
4 files changed, 50 insertions(+), 28 deletions(-)
diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
index c68e694..f0de768 100644
--- a/drivers/acpi/irq.c
+++ b/drivers/acpi/irq.c
@@ -12,7 +12,7 @@
enum acpi_irq_model_id acpi_irq_model;
-static struct fwnode_handle *acpi_gsi_domain_id;
+static struct fwnode_handle *(*acpi_get_gsi_domain_id)(u32 gsi);
/**
* acpi_gsi_to_irq() - Retrieve the linux irq number for a given GSI
@@ -26,9 +26,10 @@
*/
int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
{
- struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
- DOMAIN_BUS_ANY);
+ struct irq_domain *d;
+ d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(gsi),
+ DOMAIN_BUS_ANY);
*irq = irq_find_mapping(d, gsi);
/*
* *irq == 0 means no mapping, that should
@@ -53,12 +54,12 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
{
struct irq_fwspec fwspec;
- if (WARN_ON(!acpi_gsi_domain_id)) {
+ fwspec.fwnode = acpi_get_gsi_domain_id(gsi);
+ if (WARN_ON(!fwspec.fwnode)) {
pr_warn("GSI: No registered irqchip, giving up\n");
return -EINVAL;
}
- fwspec.fwnode = acpi_gsi_domain_id;
fwspec.param[0] = gsi;
fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
fwspec.param_count = 2;
@@ -73,13 +74,14 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
*/
void acpi_unregister_gsi(u32 gsi)
{
- struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
- DOMAIN_BUS_ANY);
+ struct irq_domain *d;
int irq;
if (WARN_ON(acpi_irq_model == ACPI_IRQ_MODEL_GIC && gsi < 16))
return;
+ d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(gsi),
+ DOMAIN_BUS_ANY);
irq = irq_find_mapping(d, gsi);
irq_dispose_mapping(irq);
}
@@ -97,7 +99,8 @@ void acpi_unregister_gsi(u32 gsi)
* The referenced device fwhandle or NULL on failure
*/
static struct fwnode_handle *
-acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source)
+acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source,
+ u32 gsi)
{
struct fwnode_handle *result;
struct acpi_device *device;
@@ -105,7 +108,7 @@ void acpi_unregister_gsi(u32 gsi)
acpi_status status;
if (!source->string_length)
- return acpi_gsi_domain_id;
+ return acpi_get_gsi_domain_id(gsi);
status = acpi_get_handle(NULL, source->string_ptr, &handle);
if (WARN_ON(ACPI_FAILURE(status)))
@@ -194,7 +197,7 @@ static acpi_status acpi_irq_parse_one_cb(struct acpi_resource *ares,
ctx->index -= irq->interrupt_count;
return AE_OK;
}
- fwnode = acpi_gsi_domain_id;
+ fwnode = acpi_get_gsi_domain_id(irq->interrupts[ctx->index]);
acpi_irq_parse_one_match(fwnode, irq->interrupts[ctx->index],
irq->triggering, irq->polarity,
irq->shareable, ctx);
@@ -207,7 +210,8 @@ static acpi_status acpi_irq_parse_one_cb(struct acpi_resource *ares,
ctx->index -= eirq->interrupt_count;
return AE_OK;
}
- fwnode = acpi_get_irq_source_fwhandle(&eirq->resource_source);
+ fwnode = acpi_get_irq_source_fwhandle(&eirq->resource_source,
+ eirq->interrupts[ctx->index]);
acpi_irq_parse_one_match(fwnode, eirq->interrupts[ctx->index],
eirq->triggering, eirq->polarity,
eirq->shareable, ctx);
@@ -291,10 +295,10 @@ int acpi_irq_get(acpi_handle handle, unsigned int index, struct resource *res)
* GSI interrupts
*/
void __init acpi_set_irq_model(enum acpi_irq_model_id model,
- struct fwnode_handle *fwnode)
+ struct fwnode_handle *(*fn)(u32))
{
acpi_irq_model = model;
- acpi_gsi_domain_id = fwnode;
+ acpi_get_gsi_domain_id = fn;
}
/**
@@ -312,8 +316,14 @@ struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
const struct irq_domain_ops *ops,
void *host_data)
{
- struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
- DOMAIN_BUS_ANY);
+ struct irq_domain *d;
+
+ /* This only works for the GIC model... */
+ if (acpi_irq_model != ACPI_IRQ_MODEL_GIC)
+ return NULL;
+
+ d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(0),
+ DOMAIN_BUS_ANY);
if (!d)
return NULL;
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 5c1cf90..c664703 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -2360,11 +2360,17 @@ static void __init gic_acpi_setup_kvm_info(void)
vgic_set_kvm_info(&gic_v3_kvm_info);
}
+static struct fwnode_handle *gsi_domain_handle;
+
+static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi)
+{
+ return gsi_domain_handle;
+}
+
static int __init
gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
{
struct acpi_madt_generic_distributor *dist;
- struct fwnode_handle *domain_handle;
size_t size;
int i, err;
@@ -2396,18 +2402,18 @@ static void __init gic_acpi_setup_kvm_info(void)
if (err)
goto out_redist_unmap;
- domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
- if (!domain_handle) {
+ gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
+ if (!gsi_domain_handle) {
err = -ENOMEM;
goto out_redist_unmap;
}
err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
- acpi_data.nr_redist_regions, 0, domain_handle);
+ acpi_data.nr_redist_regions, 0, gsi_domain_handle);
if (err)
goto out_fwhandle_free;
- acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
+ acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v3_get_gsi_domain_id);
if (static_branch_likely(&supports_deactivate_key))
gic_acpi_setup_kvm_info();
@@ -2415,7 +2421,7 @@ static void __init gic_acpi_setup_kvm_info(void)
return 0;
out_fwhandle_free:
- irq_domain_free_fwnode(domain_handle);
+ irq_domain_free_fwnode(gsi_domain_handle);
out_redist_unmap:
for (i = 0; i < acpi_data.nr_redist_regions; i++)
if (acpi_data.redist_regs[i].redist_base)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 820404c..4c7bae0 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1682,11 +1682,17 @@ static void __init gic_acpi_setup_kvm_info(void)
vgic_set_kvm_info(&gic_v2_kvm_info);
}
+static struct fwnode_handle *gsi_domain_handle;
+
+static struct fwnode_handle *gic_v2_get_gsi_domain_id(u32 gsi)
+{
+ return gsi_domain_handle;
+}
+
static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
const unsigned long end)
{
struct acpi_madt_generic_distributor *dist;
- struct fwnode_handle *domain_handle;
struct gic_chip_data *gic = &gic_data[0];
int count, ret;
@@ -1724,22 +1730,22 @@ static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
/*
* Initialize GIC instance zero (no multi-GIC support).
*/
- domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
- if (!domain_handle) {
+ gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
+ if (!gsi_domain_handle) {
pr_err("Unable to allocate domain handle\n");
gic_teardown(gic);
return -ENOMEM;
}
- ret = __gic_init_bases(gic, domain_handle);
+ ret = __gic_init_bases(gic, gsi_domain_handle);
if (ret) {
pr_err("Failed to initialise GIC\n");
- irq_domain_free_fwnode(domain_handle);
+ irq_domain_free_fwnode(gsi_domain_handle);
gic_teardown(gic);
return ret;
}
- acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
+ acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v2_get_gsi_domain_id);
if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
gicv2m_init(NULL, gic_data[0].domain);
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 4f82a5b..957e23f 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -356,7 +356,7 @@ static inline bool acpi_sci_irq_valid(void)
int acpi_isa_irq_to_gsi (unsigned isa_irq, u32 *gsi);
void acpi_set_irq_model(enum acpi_irq_model_id model,
- struct fwnode_handle *fwnode);
+ struct fwnode_handle *(*)(u32));
struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
unsigned int size,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 02/13] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 01/13] APCI: irq: Add support for multiple GSI domains Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-28 13:26 ` Hanjun Guo
2022-06-27 11:39 ` [PATCH V13 03/13] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
` (10 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
From: Marc Zyngier <maz@kernel.org>
It appears that the generic version of acpi_gsi_to_irq() doesn't
fallback to establishing a mapping if there is no pre-existing
one while the x86 version does.
While arm64 seems unaffected by it, LoongArch is relying on the x86
behaviour. In an effort to prevent new architectures from reinventing
the proverbial wheel, provide an optional callback that the arch code
can set to restore the x86 behaviour.
Hopefully we can eventually get rid of this in the future once
the expected behaviour has been clarified.
Reported-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/acpi/irq.c | 18 ++++++++++++++++--
include/linux/acpi.h | 1 +
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
index f0de768..cd87e0b 100644
--- a/drivers/acpi/irq.c
+++ b/drivers/acpi/irq.c
@@ -13,6 +13,7 @@
enum acpi_irq_model_id acpi_irq_model;
static struct fwnode_handle *(*acpi_get_gsi_domain_id)(u32 gsi);
+static int (*acpi_gsi_to_irq_fallback)(u32 gsi);
/**
* acpi_gsi_to_irq() - Retrieve the linux irq number for a given GSI
@@ -32,9 +33,12 @@ int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
DOMAIN_BUS_ANY);
*irq = irq_find_mapping(d, gsi);
/*
- * *irq == 0 means no mapping, that should
- * be reported as a failure
+ * *irq == 0 means no mapping, that should be reported as a
+ * failure, unless there is an arch-specific fallback handler.
*/
+ if (!*irq && acpi_gsi_to_irq_fallback)
+ *irq = acpi_gsi_to_irq_fallback(gsi);
+
return (*irq > 0) ? 0 : -EINVAL;
}
EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
@@ -302,6 +306,16 @@ void __init acpi_set_irq_model(enum acpi_irq_model_id model,
}
/**
+ * acpi_set_gsi_to_irq_fallback - Register a GSI transfer
+ * callback to fallback to arch specified implementation.
+ * @fn: arch-specific fallback handler
+ */
+void __init acpi_set_gsi_to_irq_fallback(int (*fn)(u32))
+{
+ acpi_gsi_to_irq_fallback = fn;
+}
+
+/**
* acpi_irq_create_hierarchy - Create a hierarchical IRQ domain with the default
* GSI domain as its parent.
* @flags: Irq domain flags associated with the domain
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 957e23f..71d3719 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -357,6 +357,7 @@ static inline bool acpi_sci_irq_valid(void)
void acpi_set_irq_model(enum acpi_irq_model_id model,
struct fwnode_handle *(*)(u32));
+void acpi_set_gsi_to_irq_fallback(int (*)(u32));
struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
unsigned int size,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 03/13] genirq/generic_chip: export irq_unmap_generic_chip
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 01/13] APCI: irq: Add support for multiple GSI domains Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 02/13] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 04/13] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
` (9 subsequent siblings)
12 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
Some irq controllers have to re-implement a private version for
irq_generic_chip_ops, because they have a different xlate to translate
hwirq. Export irq_unmap_generic_chip for reusing in user defined
ops.
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 5053082..83a4574 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -1121,6 +1121,7 @@ struct irq_domain_chip_generic {
/* Setup functions for irq_chip_generic */
int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw_irq);
+void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq);
struct irq_chip_generic *
irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
void __iomem *reg_base, irq_flow_handler_t handler);
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index f0862eb..c653cd3 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -431,7 +431,7 @@ int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
return 0;
}
-static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
+void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
{
struct irq_data *data = irq_domain_get_irq_data(d, virq);
struct irq_domain_chip_generic *dgc = d->gc;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 04/13] LoongArch: Use ACPI_GENERIC_GSI for gsi handling
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (2 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 03/13] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 05/13] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
` (8 subsequent siblings)
12 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
For LoongArch, generic gsi code(driver/acpi/irq.c) can be
reused after following patchs:
APCI: irq: Add support for multiple GSI domains
ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
So, config ACPI_GENERIC_GSI for LoongArch with removing the gsi code
in arch directory.
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
arch/loongarch/Kconfig | 1 +
arch/loongarch/kernel/acpi.c | 65 --------------------------------------------
2 files changed, 1 insertion(+), 65 deletions(-)
diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 1920d52..7f98fc0 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -112,6 +112,7 @@ config LOONGARCH
select TRACE_IRQFLAGS_SUPPORT
select USE_PERCPU_NUMA_NODE_ID
select ZONE_DMA32
+ select ACPI_GENERIC_GSI if ACPI
config 32BIT
bool
diff --git a/arch/loongarch/kernel/acpi.c b/arch/loongarch/kernel/acpi.c
index bb729ee..03aa145 100644
--- a/arch/loongarch/kernel/acpi.c
+++ b/arch/loongarch/kernel/acpi.c
@@ -25,7 +25,6 @@
int acpi_strict = 1; /* We have no workarounds on LoongArch */
int num_processors;
int disabled_cpus;
-enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_PLATFORM;
u64 acpi_saved_sp;
@@ -33,70 +32,6 @@
#define PREFIX "ACPI: "
-int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp)
-{
- if (irqp != NULL)
- *irqp = acpi_register_gsi(NULL, gsi, -1, -1);
- return (*irqp >= 0) ? 0 : -EINVAL;
-}
-EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
-
-int acpi_isa_irq_to_gsi(unsigned int isa_irq, u32 *gsi)
-{
- if (gsi)
- *gsi = isa_irq;
- return 0;
-}
-
-/*
- * success: return IRQ number (>=0)
- * failure: return < 0
- */
-int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
-{
- struct irq_fwspec fwspec;
-
- switch (gsi) {
- case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
- fwspec.fwnode = liointc_domain->fwnode;
- fwspec.param[0] = gsi - GSI_MIN_CPU_IRQ;
- fwspec.param_count = 1;
-
- return irq_create_fwspec_mapping(&fwspec);
-
- case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
- if (!pch_lpc_domain)
- return -EINVAL;
-
- fwspec.fwnode = pch_lpc_domain->fwnode;
- fwspec.param[0] = gsi - GSI_MIN_LPC_IRQ;
- fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
- fwspec.param_count = 2;
-
- return irq_create_fwspec_mapping(&fwspec);
-
- case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
- if (!pch_pic_domain[0])
- return -EINVAL;
-
- fwspec.fwnode = pch_pic_domain[0]->fwnode;
- fwspec.param[0] = gsi - GSI_MIN_PCH_IRQ;
- fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
- fwspec.param_count = 2;
-
- return irq_create_fwspec_mapping(&fwspec);
- }
-
- return -EINVAL;
-}
-EXPORT_SYMBOL_GPL(acpi_register_gsi);
-
-void acpi_unregister_gsi(u32 gsi)
-{
-
-}
-EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
-
void __init __iomem * __acpi_map_table(unsigned long phys, unsigned long size)
{
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 05/13] irqchip: Add Loongson PCH LPC controller support
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (3 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 04/13] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-29 10:58 ` Marc Zyngier
2022-06-27 11:39 ` [PATCH V13 06/13] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
` (7 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
PCH-LPC stands for "LPC Interrupts" that described in Section 24.3 of
"Loongson 7A1000 Bridge User Manual". For more information please refer
Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 4 +-
arch/loongarch/kernel/irq.c | 1 -
drivers/irqchip/Kconfig | 8 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-pch-lpc.c | 203 +++++++++++++++++++++++++++++++++
5 files changed, 214 insertions(+), 3 deletions(-)
create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index ace3ea6..48c0ce4 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -104,7 +104,7 @@ struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
-struct irq_domain *pch_lpc_acpi_init(struct irq_domain *parent,
+int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
struct acpi_madt_msi_pic *acpi_pchmsi);
@@ -121,7 +121,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
extern struct irq_domain *cpu_domain;
extern struct irq_domain *liointc_domain;
-extern struct irq_domain *pch_lpc_domain;
+extern struct fwnode_handle *pch_lpc_handle;
extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index b34b8d7..07d6059 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -27,7 +27,6 @@
struct irq_domain *cpu_domain;
struct irq_domain *liointc_domain;
-struct irq_domain *pch_lpc_domain;
struct irq_domain *pch_msi_domain[MAX_IO_PICS];
struct irq_domain *pch_pic_domain[MAX_IO_PICS];
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 1f23a6b..c1d527f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -591,6 +591,14 @@ config LOONGSON_PCH_MSI
help
Support for the Loongson PCH MSI Controller.
+config LOONGSON_PCH_LPC
+ bool "Loongson PCH LPC Controller"
+ depends on MACH_LOONGSON64
+ default (MACH_LOONGSON64 && LOONGARCH)
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Support for the Loongson PCH LPC Controller.
+
config MST_IRQ
bool "MStar Interrupt Controller"
depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 5b67450..242b8b3 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
+obj-$(CONFIG_LOONGSON_PCH_LPC) += irq-loongson-pch-lpc.o
obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o
obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
new file mode 100644
index 0000000..7e4d89a
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson LPC Interrupt Controller support
+ *
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#define pr_fmt(fmt) "lpc: " fmt
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+
+/* Registers */
+#define LPC_INT_CTL 0x00
+#define LPC_INT_ENA 0x04
+#define LPC_INT_STS 0x08
+#define LPC_INT_CLR 0x0c
+#define LPC_INT_POL 0x10
+#define LPC_COUNT 16
+
+struct pch_lpc {
+ void __iomem *base;
+ struct irq_domain *lpc_domain;
+ raw_spinlock_t lpc_lock;
+ u32 saved_reg_ctl;
+ u32 saved_reg_ena;
+ u32 saved_reg_pol;
+};
+
+struct fwnode_handle *pch_lpc_handle;
+
+static void ack_lpc_irq(struct irq_data *d)
+{
+ unsigned long flags;
+ struct pch_lpc *priv = d->domain->host_data;
+
+ raw_spin_lock_irqsave(&priv->lpc_lock, flags);
+ writel(0x1 << d->hwirq, priv->base + LPC_INT_CLR);
+ raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
+}
+static void mask_lpc_irq(struct irq_data *d)
+{
+ unsigned long flags;
+ struct pch_lpc *priv = d->domain->host_data;
+
+ raw_spin_lock_irqsave(&priv->lpc_lock, flags);
+ writel(readl(priv->base + LPC_INT_ENA) & (~(0x1 << (d->hwirq))),
+ priv->base + LPC_INT_ENA);
+ raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
+}
+
+static void unmask_lpc_irq(struct irq_data *d)
+{
+ unsigned long flags;
+ struct pch_lpc *priv = d->domain->host_data;
+
+ raw_spin_lock_irqsave(&priv->lpc_lock, flags);
+ writel(readl(priv->base + LPC_INT_ENA) | (0x1 << (d->hwirq)),
+ priv->base + LPC_INT_ENA);
+ raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
+}
+
+static int lpc_set_type(struct irq_data *d, unsigned int type)
+{
+ u32 val;
+ u32 mask = 0x1 << (d->hwirq);
+ struct pch_lpc *priv = d->domain->host_data;
+
+ if (!(type & IRQ_TYPE_LEVEL_MASK))
+ return 0;
+
+ val = readl(priv->base + LPC_INT_POL);
+
+ if (type == IRQ_TYPE_LEVEL_HIGH)
+ val |= mask;
+ else
+ val &= ~mask;
+
+ writel(val, priv->base + LPC_INT_POL);
+
+ return 0;
+}
+
+static struct irq_chip pch_lpc_irq_chip = {
+ .name = "PCH LPC",
+ .irq_mask = mask_lpc_irq,
+ .irq_unmask = unmask_lpc_irq,
+ .irq_ack = ack_lpc_irq,
+ .irq_set_type = lpc_set_type,
+ .flags = IRQCHIP_SKIP_SET_WAKE,
+};
+
+static void lpc_irq_dispatch(struct irq_desc *desc)
+{
+ u32 pending, bit, virq;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct pch_lpc *priv = irq_desc_get_handler_data(desc);
+
+ chained_irq_enter(chip, desc);
+
+ pending = readl(priv->base + LPC_INT_ENA);
+ pending &= readl(priv->base + LPC_INT_STS);
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ bit = __ffs(pending);
+ virq = irq_linear_revmap(priv->lpc_domain, bit);
+
+ generic_handle_irq(bit);
+ pending &= ~BIT(bit);
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static int pch_lpc_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ irq_set_chip_and_handler(irq, &pch_lpc_irq_chip, handle_level_irq);
+ return 0;
+}
+
+static const struct irq_domain_ops pch_lpc_domain_ops = {
+ .map = pch_lpc_map,
+ .translate = irq_domain_translate_twocell,
+};
+
+static void pch_lpc_reset(struct pch_lpc *priv)
+{
+ /* Enable the LPC interrupt, bit31: en bit30: edge */
+ writel(0x80000000, priv->base + LPC_INT_CTL);
+ writel(0, priv->base + LPC_INT_ENA);
+ /* Clear all 18-bit interrpt bit */
+ writel(0x3ffff, priv->base + LPC_INT_CLR);
+}
+
+static int pch_lpc_disabled(struct pch_lpc *priv)
+{
+ return (readl(priv->base + LPC_INT_ENA) == 0xffffffff) &&
+ (readl(priv->base + LPC_INT_STS) == 0xffffffff);
+}
+
+int __init pch_lpc_acpi_init(struct irq_domain *parent,
+ struct acpi_madt_lpc_pic *acpi_pchlpc)
+{
+ int parent_irq;
+ struct pch_lpc *priv;
+ struct irq_fwspec fwspec;
+ struct fwnode_handle *irq_handle;
+
+ if (!acpi_pchlpc)
+ return -EINVAL;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ raw_spin_lock_init(&priv->lpc_lock);
+
+ priv->base = ioremap(acpi_pchlpc->address, acpi_pchlpc->size);
+ if (!priv->base)
+ goto free_priv;
+
+ if (pch_lpc_disabled(priv)) {
+ pr_err("Failed to get LPC status\n");
+ goto iounmap_base;
+ }
+
+ irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
+ if (!irq_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ goto iounmap_base;
+ }
+
+ priv->lpc_domain = irq_domain_create_linear(irq_handle, LPC_COUNT,
+ &pch_lpc_domain_ops, priv);
+ if (!priv->lpc_domain) {
+ pr_err("Failed to create IRQ domain\n");
+ goto iounmap_base;
+ }
+ pch_lpc_reset(priv);
+
+ fwspec.fwnode = parent->fwnode;
+ fwspec.param[0] = acpi_pchlpc->cascade;
+ fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
+ fwspec.param_count = 2;
+ parent_irq = irq_create_fwspec_mapping(&fwspec);
+ irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv);
+
+ pch_lpc_handle = irq_handle;
+ return 0;
+
+iounmap_base:
+ iounmap(priv->base);
+free_priv:
+ kfree(priv);
+
+ return -ENOMEM;
+}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 06/13] irqchip/loongson-pch-pic: Add ACPI init support
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (4 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 05/13] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-29 11:20 ` Marc Zyngier
2022-06-27 11:39 ` [PATCH V13 07/13] irqchip/loongson-pch-msi: " Jianmin Lv
` (6 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
We are preparing to add new Loongson (based on LoongArch, not compatible
with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
as its boot protocol, so add ACPI init support.
PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
please refer Documentation/loongarch/irq-chip-model.rst.
For systems with two chipsets, there are two related pch irqdomains,
each of which has the same node id as its parent irqdomain. So we
defined a structure to mantain the relation of node and it's parent
irqdomain.
struct acpi_vector_group {
int node;
struct irq_domain *parent;
};
The parent irqdomain will be set for node id in parent irqdomain driver
before pch irqdomain is created.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 11 +-
arch/loongarch/kernel/irq.c | 2 +-
drivers/irqchip/irq-loongson-pch-pic.c | 200 ++++++++++++++++++++++++++++-----
3 files changed, 179 insertions(+), 34 deletions(-)
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 48c0ce4..a444dc6 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -48,6 +48,12 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
#define MAX_IO_PICS 2
#define NR_IRQS (64 + (256 * MAX_IO_PICS))
+struct acpi_vector_group {
+ int node;
+ struct irq_domain *parent;
+};
+extern struct acpi_vector_group pch_group[MAX_IO_PICS];
+
#define CORES_PER_EIO_NODE 4
#define LOONGSON_CPU_UART0_VEC 10 /* CPU UART0 */
@@ -108,8 +114,7 @@ int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
struct acpi_madt_msi_pic *acpi_pchmsi);
-struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
- struct acpi_madt_bio_pic *acpi_pchpic);
+int find_pch_pic(u32 gsi);
extern struct acpi_madt_lio_pic *acpi_liointc;
extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
@@ -123,7 +128,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
extern struct irq_domain *liointc_domain;
extern struct fwnode_handle *pch_lpc_handle;
extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
-extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
+extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 07d6059..f2115be 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -28,7 +28,7 @@
struct irq_domain *cpu_domain;
struct irq_domain *liointc_domain;
struct irq_domain *pch_msi_domain[MAX_IO_PICS];
-struct irq_domain *pch_pic_domain[MAX_IO_PICS];
+struct acpi_vector_group pch_group[MAX_IO_PICS];
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
index a4eb8a2..170a5b9 100644
--- a/drivers/irqchip/irq-loongson-pch-pic.c
+++ b/drivers/irqchip/irq-loongson-pch-pic.c
@@ -33,13 +33,40 @@
#define PIC_REG_IDX(irq_id) ((irq_id) / PIC_COUNT_PER_REG)
#define PIC_REG_BIT(irq_id) ((irq_id) % PIC_COUNT_PER_REG)
+static int nr_pics;
+
struct pch_pic {
void __iomem *base;
struct irq_domain *pic_domain;
+ struct fwnode_handle *domain_handle;
u32 ht_vec_base;
raw_spinlock_t pic_lock;
+ u32 gsi_end;
+ u32 gsi_base;
};
+static struct pch_pic *pch_pic_priv[2];
+struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
+
+int find_pch_pic(u32 gsi)
+{
+ int i;
+
+ /* Find the PCH_PIC that manages this GSI. */
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ struct pch_pic *priv = pch_pic_priv[i];
+
+ if (!priv)
+ return -1;
+
+ if (gsi >= priv->gsi_base && gsi <= priv->gsi_end)
+ return i;
+ }
+
+ pr_err("ERROR: Unable to locate PCH_PIC for GSI %d\n", gsi);
+ return -1;
+}
+
static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)
{
u32 reg;
@@ -139,6 +166,24 @@ static void pch_pic_ack_irq(struct irq_data *d)
.irq_set_type = pch_pic_set_type,
};
+static int pch_pic_domain_translate(struct irq_domain *d,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ struct pch_pic *priv = d->host_data;
+ struct device_node *of_node = to_of_node(fwspec->fwnode);
+
+ if (fwspec->param_count < 1)
+ return -EINVAL;
+ if (of_node)
+ *hwirq += priv->ht_vec_base;
+ else
+ *hwirq = fwspec->param[0] - priv->gsi_base;
+ *type = IRQ_TYPE_NONE;
+
+ return 0;
+}
static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
@@ -149,13 +194,13 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
struct irq_fwspec parent_fwspec;
struct pch_pic *priv = domain->host_data;
- err = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
+ err = pch_pic_domain_translate(domain, fwspec, &hwirq, &type);
if (err)
return err;
parent_fwspec.fwnode = domain->parent->fwnode;
parent_fwspec.param_count = 1;
- parent_fwspec.param[0] = hwirq + priv->ht_vec_base;
+ parent_fwspec.param[0] = hwirq;
err = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
if (err)
@@ -170,7 +215,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
}
static const struct irq_domain_ops pch_pic_domain_ops = {
- .translate = irq_domain_translate_twocell,
+ .translate = pch_pic_domain_translate,
.alloc = pch_pic_alloc,
.free = irq_domain_free_irqs_parent,
};
@@ -180,7 +225,7 @@ static void pch_pic_reset(struct pch_pic *priv)
int i;
for (i = 0; i < PIC_COUNT; i++) {
- /* Write vectored ID */
+ /* Write vector ID */
writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i));
/* Hardcode route to HT0 Lo */
writeb(1, priv->base + PCH_INT_ROUTE(i));
@@ -198,50 +243,41 @@ static void pch_pic_reset(struct pch_pic *priv)
}
}
-static int pch_pic_of_init(struct device_node *node,
- struct device_node *parent)
+static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base,
+ struct irq_domain *parent_domain, struct fwnode_handle *domain_handle,
+ u32 gsi_base)
{
+ int vec_count;
struct pch_pic *priv;
- struct irq_domain *parent_domain;
- int err;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
raw_spin_lock_init(&priv->pic_lock);
- priv->base = of_iomap(node, 0);
- if (!priv->base) {
- err = -ENOMEM;
+ priv->base = ioremap(addr, size);
+ if (!priv->base)
goto free_priv;
- }
- parent_domain = irq_find_host(parent);
- if (!parent_domain) {
- pr_err("Failed to find the parent domain\n");
- err = -ENXIO;
- goto iounmap_base;
- }
+ priv->domain_handle = domain_handle;
- if (of_property_read_u32(node, "loongson,pic-base-vec",
- &priv->ht_vec_base)) {
- pr_err("Failed to determine pic-base-vec\n");
- err = -EINVAL;
- goto iounmap_base;
- }
+ priv->ht_vec_base = vec_base;
+ vec_count = ((readq(priv->base) >> 48) & 0xff) + 1;
+ priv->gsi_base = gsi_base;
+ priv->gsi_end = gsi_base + vec_count - 1;
priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0,
- PIC_COUNT,
- of_node_to_fwnode(node),
- &pch_pic_domain_ops,
- priv);
+ vec_count, priv->domain_handle,
+ &pch_pic_domain_ops, priv);
+
if (!priv->pic_domain) {
pr_err("Failed to create IRQ domain\n");
- err = -ENOMEM;
goto iounmap_base;
}
pch_pic_reset(priv);
+ pch_pic_handle[nr_pics] = domain_handle;
+ pch_pic_priv[nr_pics++] = priv;
return 0;
@@ -250,7 +286,111 @@ static int pch_pic_of_init(struct device_node *node,
free_priv:
kfree(priv);
- return err;
+ return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+
+static int pch_pic_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ int err, vec_base;
+ struct resource res;
+ struct irq_domain *parent_domain;
+
+ if (of_address_to_resource(node, 0, &res))
+ return -EINVAL;
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ pr_err("Failed to find the parent domain\n");
+ return -ENXIO;
+ }
+
+ if (of_property_read_u32(node, "loongson,pic-base-vec", &vec_base)) {
+ pr_err("Failed to determine pic-base-vec\n");
+ return -EINVAL;
+ }
+
+ err = pch_pic_init(res.start, resource_size(&res), vec_base,
+ parent_domain, of_node_to_fwnode(node), 0);
+ if (err < 0)
+ return err;
+
+ return 0;
}
IRQCHIP_DECLARE(pch_pic, "loongson,pch-pic-1.0", pch_pic_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+static int __init
+lpcintc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_lpc_pic *lpcintc_entry = (struct acpi_madt_lpc_pic *)header;
+
+ return pch_lpc_acpi_init(pch_pic_priv[0]->pic_domain, lpcintc_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_LPC_PIC,
+ lpcintc_parse_madt, 0);
+ return 0;
+}
+int __init pch_pic_init_irqdomain(struct irq_domain *parent,
+ struct acpi_madt_bio_pic *acpi_pchpic)
+{
+ int ret, vec_base;
+ struct fwnode_handle *domain_handle;
+
+ if (!acpi_pchpic)
+ return -EINVAL;
+
+ vec_base = acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ;
+
+ domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchpic);
+ if (!domain_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ return -ENOMEM;
+ }
+
+ ret = pch_pic_init(acpi_pchpic->address, acpi_pchpic->size,
+ vec_base, parent, domain_handle, acpi_pchpic->gsi_base);
+ if (ret == 0 && acpi_pchpic->id == 0)
+ acpi_cascade_irqdomain_init();
+
+ return ret;
+}
+
+struct irq_domain *acpi_get_pch_parent(int node)
+{
+ int i;
+
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ if (node == pch_group[i].node)
+ return pch_group[i].parent;
+ }
+ return NULL;
+}
+
+static int __init pchintc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_bio_pic *pch_pic_entry = (struct acpi_madt_bio_pic *)header;
+
+ return pch_pic_init_irqdomain(acpi_get_pch_parent((pch_pic_entry->address >> 44) & 0xf),
+ pch_pic_entry);
+}
+
+static int __init pch_pic_acpi_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
+ pchintc_parse_madt, 0);
+
+ return 0;
+}
+early_initcall(pch_pic_acpi_init);
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 07/13] irqchip/loongson-pch-msi: Add ACPI init support
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (5 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 06/13] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-29 13:15 ` Marc Zyngier
2022-06-27 11:39 ` [PATCH V13 08/13] irqchip/loongson-htvec: " Jianmin Lv
` (5 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
We are preparing to add new Loongson (based on LoongArch, not compatible
with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
as its boot protocol, so add ACPI init support.
PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
please refer Documentation/loongarch/irq-chip-model.rst.
For systems with two chipsets, there are two related msi irqdomains,
each of which has the same node id as its parent irqdomain. So we
use a structure to mantain the relation of node and it's parent
irqdomain as pch irqdomin, and add a pci_segment field to it for
matching the pci segment of a pci device when setting msi irqdomain
for the device.
struct acpi_vector_group {
int node;
int pci_segment;
struct irq_domain *parent;
};
The field 'pci_segment' and 'node' are initialized from MCFG, and
the parent irqdomain will set field 'parent' by matching same
'node'.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 7 +-
arch/loongarch/kernel/irq.c | 30 ++++++-
drivers/irqchip/irq-loongson-pch-msi.c | 147 +++++++++++++++++++++++----------
3 files changed, 138 insertions(+), 46 deletions(-)
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index a444dc6..367aa44 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -50,9 +50,11 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
struct acpi_vector_group {
int node;
+ int pci_segment;
struct irq_domain *parent;
};
extern struct acpi_vector_group pch_group[MAX_IO_PICS];
+extern struct acpi_vector_group msi_group[MAX_IO_PICS];
#define CORES_PER_EIO_NODE 4
@@ -112,9 +114,8 @@ struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
-struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
- struct acpi_madt_msi_pic *acpi_pchmsi);
int find_pch_pic(u32 gsi);
+struct fwnode_handle *get_pch_msi_handle(int pci_segment);
extern struct acpi_madt_lio_pic *acpi_liointc;
extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
@@ -127,7 +128,7 @@ struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
extern struct irq_domain *cpu_domain;
extern struct irq_domain *liointc_domain;
extern struct fwnode_handle *pch_lpc_handle;
-extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
+extern struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index f2115be..82bc6c7 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -27,8 +27,8 @@
struct irq_domain *cpu_domain;
struct irq_domain *liointc_domain;
-struct irq_domain *pch_msi_domain[MAX_IO_PICS];
struct acpi_vector_group pch_group[MAX_IO_PICS];
+struct acpi_vector_group msi_group[MAX_IO_PICS];
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
@@ -55,6 +55,33 @@ int arch_show_interrupts(struct seq_file *p, int prec)
return 0;
}
+static int early_pci_mcfg_parse(struct acpi_table_header *header)
+{
+ struct acpi_table_mcfg *mcfg;
+ struct acpi_mcfg_allocation *mptr;
+ int i, n;
+
+ if (header->length < sizeof(struct acpi_table_mcfg))
+ return -EINVAL;
+
+ n = (header->length - sizeof(struct acpi_table_mcfg)) /
+ sizeof(struct acpi_mcfg_allocation);
+ mcfg = (struct acpi_table_mcfg *)header;
+ mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
+
+ for (i = 0; i < n; i++, mptr++) {
+ msi_group[i].pci_segment = mptr->pci_segment;
+ msi_group[i].node = (mptr->address >> 44) & 0xf;
+ }
+
+ return 0;
+}
+
+void __init init_msi_parent_group(void)
+{
+ acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
+}
+
void __init init_IRQ(void)
{
int i;
@@ -68,6 +95,7 @@ void __init init_IRQ(void)
clear_csr_ecfg(ECFG0_IM);
clear_csr_estat(ESTATF_IP);
+ init_msi_parent_group();
irqchip_init();
#ifdef CONFIG_SMP
ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-loongson-pch-msi.c
index e3801c4..5db4a68 100644
--- a/drivers/irqchip/irq-loongson-pch-msi.c
+++ b/drivers/irqchip/irq-loongson-pch-msi.c
@@ -15,14 +15,30 @@
#include <linux/pci.h>
#include <linux/slab.h>
+static int nr_pics;
+
struct pch_msi_data {
struct mutex msi_map_lock;
phys_addr_t doorbell;
u32 irq_first; /* The vector number that MSIs starts */
u32 num_irqs; /* The number of vectors for MSIs */
unsigned long *msi_map;
+ struct fwnode_handle *domain_handle;
};
+static struct pch_msi_data *pch_msi_priv[2];
+
+struct fwnode_handle *get_pch_msi_handle(int pci_segment)
+{
+ int i;
+
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ if (msi_group[i].pci_segment == pci_segment)
+ return pch_msi_priv[i]->domain_handle;
+ }
+ return NULL;
+}
+
static void pch_msi_mask_msi_irq(struct irq_data *d)
{
pci_msi_mask_irq(d);
@@ -154,12 +170,14 @@ static void pch_msi_middle_domain_free(struct irq_domain *domain,
};
static int pch_msi_init_domains(struct pch_msi_data *priv,
- struct device_node *node,
- struct irq_domain *parent)
+ struct irq_domain *parent,
+ struct fwnode_handle *domain_handle)
{
struct irq_domain *middle_domain, *msi_domain;
- middle_domain = irq_domain_create_linear(of_node_to_fwnode(node),
+ priv->domain_handle = domain_handle;
+
+ middle_domain = irq_domain_create_linear(priv->domain_handle,
priv->num_irqs,
&pch_msi_middle_domain_ops,
priv);
@@ -171,7 +189,7 @@ static int pch_msi_init_domains(struct pch_msi_data *priv,
middle_domain->parent = parent;
irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS);
- msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
+ msi_domain = pci_msi_create_irq_domain(priv->domain_handle,
&pch_msi_domain_info,
middle_domain);
if (!msi_domain) {
@@ -183,19 +201,11 @@ static int pch_msi_init_domains(struct pch_msi_data *priv,
return 0;
}
-static int pch_msi_init(struct device_node *node,
- struct device_node *parent)
+static int pch_msi_init(phys_addr_t msg_address, int irq_base, int irq_count,
+ struct irq_domain *parent_domain, struct fwnode_handle *domain_handle)
{
- struct pch_msi_data *priv;
- struct irq_domain *parent_domain;
- struct resource res;
int ret;
-
- parent_domain = irq_find_host(parent);
- if (!parent_domain) {
- pr_err("Failed to find the parent domain\n");
- return -ENXIO;
- }
+ struct pch_msi_data *priv;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -203,48 +213,101 @@ static int pch_msi_init(struct device_node *node,
mutex_init(&priv->msi_map_lock);
- ret = of_address_to_resource(node, 0, &res);
- if (ret) {
- pr_err("Failed to allocate resource\n");
- goto err_priv;
- }
-
- priv->doorbell = res.start;
-
- if (of_property_read_u32(node, "loongson,msi-base-vec",
- &priv->irq_first)) {
- pr_err("Unable to parse MSI vec base\n");
- ret = -EINVAL;
- goto err_priv;
- }
-
- if (of_property_read_u32(node, "loongson,msi-num-vecs",
- &priv->num_irqs)) {
- pr_err("Unable to parse MSI vec number\n");
- ret = -EINVAL;
- goto err_priv;
- }
+ priv->doorbell = msg_address;
+ priv->irq_first = irq_base;
+ priv->num_irqs = irq_count;
priv->msi_map = bitmap_zalloc(priv->num_irqs, GFP_KERNEL);
- if (!priv->msi_map) {
- ret = -ENOMEM;
+ if (!priv->msi_map)
goto err_priv;
- }
pr_debug("Registering %d MSIs, starting at %d\n",
priv->num_irqs, priv->irq_first);
- ret = pch_msi_init_domains(priv, node, parent_domain);
+ ret = pch_msi_init_domains(priv, parent_domain, domain_handle);
if (ret)
goto err_map;
+ pch_msi_priv[nr_pics++] = priv;
return 0;
err_map:
bitmap_free(priv->msi_map);
err_priv:
kfree(priv);
- return ret;
+
+ return -EINVAL;
}
-IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_init);
+#ifdef CONFIG_OF
+
+static int pch_msi_of_init(struct device_node *node, struct device_node *parent)
+{
+ int err;
+ int irq_base, irq_count;
+ struct resource res;
+ struct irq_domain *parent_domain;
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ pr_err("Failed to find the parent domain\n");
+ return -ENXIO;
+ }
+
+ if (of_address_to_resource(node, 0, &res)) {
+ pr_err("Failed to allocate resource\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "loongson,msi-base-vec", &irq_base)) {
+ pr_err("Unable to parse MSI vec base\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "loongson,msi-num-vecs", &irq_count)) {
+ pr_err("Unable to parse MSI vec number\n");
+ return -EINVAL;
+ }
+
+ err = pch_msi_init(res.start, irq_base, irq_count, parent_domain, of_node_to_fwnode(node));
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+int __init pch_msi_init_irqdomain(struct irq_domain *parent,
+ struct acpi_madt_msi_pic *acpi_pchmsi)
+{
+ struct fwnode_handle *domain_handle;
+
+ if (!acpi_pchmsi)
+ return -EINVAL;
+
+ domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchmsi);
+
+ return pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start,
+ acpi_pchmsi->count, parent, domain_handle);
+}
+static int __init msiintc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_msi_pic *pch_msi_entry = (struct acpi_madt_msi_pic *)header;
+
+ return pch_msi_init_irqdomain(msi_group[nr_pics].parent, pch_msi_entry);
+}
+
+static int __init pch_msi_acpi_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
+ msiintc_parse_madt, 0);
+
+ return 0;
+}
+early_initcall(pch_msi_acpi_init);
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 08/13] irqchip/loongson-htvec: Add ACPI init support
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (6 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 07/13] irqchip/loongson-pch-msi: " Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 09/13] irqchip/loongson-liointc: " Jianmin Lv
` (4 subsequent siblings)
12 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
We are preparing to add new Loongson (based on LoongArch, not compatible
with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
as its boot protocol, so add ACPI init support.
HTVECINTC stands for "HyperTransport Interrupts" that described in
Section 14.3 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 2 +-
drivers/irqchip/irq-loongson-htvec.c | 121 +++++++++++++++++++++++++----------
2 files changed, 88 insertions(+), 35 deletions(-)
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 367aa44..e1e9e04 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -110,7 +110,7 @@ struct irq_domain *liointc_acpi_init(struct irq_domain *parent,
struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_eio_pic *acpi_eiointc);
-struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
+int htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c
index 60a335d..74e7896 100644
--- a/drivers/irqchip/irq-loongson-htvec.c
+++ b/drivers/irqchip/irq-loongson-htvec.c
@@ -20,7 +20,6 @@
/* Registers */
#define HTVEC_EN_OFF 0x20
#define HTVEC_MAX_PARENT_IRQ 8
-
#define VEC_COUNT_PER_REG 32
#define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
#define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
@@ -30,8 +29,11 @@ struct htvec {
void __iomem *base;
struct irq_domain *htvec_domain;
raw_spinlock_t htvec_lock;
+ struct fwnode_handle *domain_handle;
};
+static struct htvec *htvec_priv;
+
static void htvec_irq_dispatch(struct irq_desc *desc)
{
int i;
@@ -155,64 +157,115 @@ static void htvec_reset(struct htvec *priv)
}
}
-static int htvec_of_init(struct device_node *node,
- struct device_node *parent)
+static int htvec_init(phys_addr_t addr, unsigned long size,
+ int num_parents, int parent_irq[], struct fwnode_handle *domain_handle)
{
+ int i;
struct htvec *priv;
- int err, parent_irq[8], i;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ priv->num_parents = num_parents;
+ priv->base = ioremap(addr, size);
+ priv->domain_handle = domain_handle;
raw_spin_lock_init(&priv->htvec_lock);
- priv->base = of_iomap(node, 0);
- if (!priv->base) {
- err = -ENOMEM;
- goto free_priv;
- }
-
- /* Interrupt may come from any of the 8 interrupt lines */
- for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
- parent_irq[i] = irq_of_parse_and_map(node, i);
- if (parent_irq[i] <= 0)
- break;
-
- priv->num_parents++;
- }
-
- if (!priv->num_parents) {
- pr_err("Failed to get parent irqs\n");
- err = -ENODEV;
- goto iounmap_base;
- }
- priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node),
+ /* Setup IRQ domain */
+ priv->htvec_domain = irq_domain_create_linear(priv->domain_handle,
(VEC_COUNT_PER_REG * priv->num_parents),
&htvec_domain_ops, priv);
if (!priv->htvec_domain) {
- pr_err("Failed to create IRQ domain\n");
- err = -ENOMEM;
- goto irq_dispose;
+ pr_err("loongson-htvec: cannot add IRQ domain\n");
+ goto iounmap_base;
}
htvec_reset(priv);
- for (i = 0; i < priv->num_parents; i++)
+ for (i = 0; i < priv->num_parents; i++) {
irq_set_chained_handler_and_data(parent_irq[i],
htvec_irq_dispatch, priv);
+ }
+
+ htvec_priv = priv;
return 0;
-irq_dispose:
- for (; i > 0; i--)
- irq_dispose_mapping(parent_irq[i - 1]);
iounmap_base:
iounmap(priv->base);
-free_priv:
+ priv->domain_handle = NULL;
kfree(priv);
- return err;
+ return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+
+static int htvec_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ int i, err;
+ int parent_irq[8];
+ int num_parents = 0;
+ struct resource res;
+
+ if (of_address_to_resource(node, 0, &res))
+ return -EINVAL;
+
+ /* Interrupt may come from any of the 8 interrupt lines */
+ for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
+ parent_irq[i] = irq_of_parse_and_map(node, i);
+ if (parent_irq[i] <= 0)
+ break;
+
+ num_parents++;
+ }
+
+ err = htvec_init(res.start, resource_size(&res),
+ num_parents, parent_irq, of_node_to_fwnode(node));
+ if (err < 0)
+ return err;
+
+ return 0;
}
IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+int __init htvec_acpi_init(struct irq_domain *parent,
+ struct acpi_madt_ht_pic *acpi_htvec)
+{
+ int i, ret;
+ int num_parents, parent_irq[8];
+ struct fwnode_handle *domain_handle;
+
+ if (!acpi_htvec)
+ return -EINVAL;
+
+ num_parents = HTVEC_MAX_PARENT_IRQ;
+
+ domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_htvec);
+ if (!domain_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ return -ENOMEM;
+ }
+
+ /* Interrupt may come from any of the 8 interrupt lines */
+ for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++)
+ parent_irq[i] = irq_create_mapping(parent, acpi_htvec->cascade[i]);
+
+ ret = htvec_init(acpi_htvec->address, acpi_htvec->size,
+ num_parents, parent_irq, domain_handle);
+ if (ret == 0) {
+ /* Only support single chipset system. */
+ msi_group[0].parent = htvec_priv->htvec_domain;
+ pch_group[0].parent = htvec_priv->htvec_domain;
+ pch_group[0].node = 0;
+ }
+ return ret;
+}
+
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 09/13] irqchip/loongson-liointc: Add ACPI init support
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (7 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 08/13] irqchip/loongson-htvec: " Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-29 13:13 ` Marc Zyngier
2022-06-27 11:39 ` [PATCH V13 10/13] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
` (3 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
We are preparing to add new Loongson (based on LoongArch, not compatible
with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
as its boot protocol, so add ACPI init support.
LIOINTC stands for "Legacy I/O Interrupts" that described in Section
11.1 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 4 +-
arch/loongarch/kernel/irq.c | 1 -
drivers/irqchip/irq-loongson-liointc.c | 227 ++++++++++++++++++++++-----------
3 files changed, 154 insertions(+), 78 deletions(-)
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index e1e9e04..fbd2bc9 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -105,7 +105,7 @@ static inline void eiointc_enable(void)
struct irq_domain *loongarch_cpu_irq_init(void);
-struct irq_domain *liointc_acpi_init(struct irq_domain *parent,
+int liointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lio_pic *acpi_liointc);
struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_eio_pic *acpi_eiointc);
@@ -126,7 +126,7 @@ int pch_lpc_acpi_init(struct irq_domain *parent,
extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
extern struct irq_domain *cpu_domain;
-extern struct irq_domain *liointc_domain;
+extern struct fwnode_handle *liointc_handle;
extern struct fwnode_handle *pch_lpc_handle;
extern struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 82bc6c7..5695826 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -26,7 +26,6 @@
EXPORT_PER_CPU_SYMBOL(irq_stat);
struct irq_domain *cpu_domain;
-struct irq_domain *liointc_domain;
struct acpi_vector_group pch_group[MAX_IO_PICS];
struct acpi_vector_group msi_group[MAX_IO_PICS];
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 8d05d8b..f690155 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -23,7 +23,7 @@
#endif
#define LIOINTC_CHIP_IRQ 32
-#define LIOINTC_NUM_PARENT 4
+#define LIOINTC_NUM_PARENT 4
#define LIOINTC_NUM_CORES 4
#define LIOINTC_INTC_CHIP_START 0x20
@@ -51,6 +51,7 @@ struct liointc_handler_data {
};
struct liointc_priv {
+ struct fwnode_handle *domain_handle;
struct irq_chip_generic *gc;
struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
void __iomem *core_isr[LIOINTC_NUM_CORES];
@@ -58,6 +59,8 @@ struct liointc_priv {
bool has_lpc_irq_errata;
};
+struct fwnode_handle *liointc_handle;
+
static void liointc_chained_handle_irq(struct irq_desc *desc)
{
struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
@@ -153,97 +156,83 @@ static void liointc_resume(struct irq_chip_generic *gc)
irq_gc_unlock_irqrestore(gc, flags);
}
-static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
-static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
+static int parent_irq[LIOINTC_NUM_PARENT];
+static u32 parent_int_map[LIOINTC_NUM_PARENT];
+static const char *const parent_names[] = {"int0", "int1", "int2", "int3"};
+static const char *const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
-static void __iomem *liointc_get_reg_byname(struct device_node *node,
- const char *name)
+static int liointc_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+ const u32 *intspec, unsigned int intsize,
+ unsigned long *out_hwirq, unsigned int *out_type)
{
- int index = of_property_match_string(node, "reg-names", name);
-
- if (index < 0)
- return NULL;
-
- return of_iomap(node, index);
+ if (WARN_ON(intsize < 1))
+ return -EINVAL;
+ *out_hwirq = intspec[0] - GSI_MIN_CPU_IRQ;
+ *out_type = IRQ_TYPE_NONE;
+ return 0;
}
-static int __init liointc_of_init(struct device_node *node,
- struct device_node *parent)
+const struct irq_domain_ops acpi_irq_gc_ops = {
+ .map = irq_map_generic_chip,
+ .unmap = irq_unmap_generic_chip,
+ .xlate = liointc_domain_xlate,
+};
+
+static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
+ struct fwnode_handle *domain_handle, struct device_node *node)
{
+ int i, err;
+ void __iomem *base;
+ struct irq_chip_type *ct;
struct irq_chip_generic *gc;
struct irq_domain *domain;
- struct irq_chip_type *ct;
struct liointc_priv *priv;
- void __iomem *base;
- u32 of_parent_int_map[LIOINTC_NUM_PARENT];
- int parent_irq[LIOINTC_NUM_PARENT];
- bool have_parent = FALSE;
- int sz, i, err = 0;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
- if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
- base = liointc_get_reg_byname(node, "main");
- if (!base) {
- err = -ENODEV;
- goto out_free_priv;
- }
+ base = ioremap(addr, size);
+ if (!base)
+ goto out_free_priv;
- for (i = 0; i < LIOINTC_NUM_CORES; i++)
- priv->core_isr[i] = liointc_get_reg_byname(node, core_reg_names[i]);
- if (!priv->core_isr[0]) {
- err = -ENODEV;
- goto out_iounmap_base;
- }
- } else {
- base = of_iomap(node, 0);
- if (!base) {
- err = -ENODEV;
- goto out_free_priv;
- }
+ priv->domain_handle = domain_handle;
- for (i = 0; i < LIOINTC_NUM_CORES; i++)
- priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
- }
+ for (i = 0; i < LIOINTC_NUM_CORES; i++)
+ priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
- for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
- parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
- if (parent_irq[i] > 0)
- have_parent = TRUE;
- }
- if (!have_parent) {
- err = -ENODEV;
- goto out_iounmap_isr;
- }
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++)
+ priv->handler[i].parent_int_map = parent_int_map[i];
- sz = of_property_read_variable_u32_array(node,
- "loongson,parent_int_map",
- &of_parent_int_map[0],
- LIOINTC_NUM_PARENT,
- LIOINTC_NUM_PARENT);
- if (sz < 4) {
- pr_err("loongson-liointc: No parent_int_map\n");
- err = -ENODEV;
- goto out_iounmap_isr;
- }
+#ifdef CONFIG_OF
+ if (revision > 1) {
+ for (i = 0; i < LIOINTC_NUM_CORES; i++) {
+ int index = of_property_match_string(node,
+ "reg-names", core_reg_names[i]);
- for (i = 0; i < LIOINTC_NUM_PARENT; i++)
- priv->handler[i].parent_int_map = of_parent_int_map[i];
+ if (index < 0)
+ return -EINVAL;
+
+ priv->core_isr[i] = of_iomap(node, index);
+ }
+ }
+#endif
/* Setup IRQ domain */
- domain = irq_domain_add_linear(node, 32,
+ if (!node)
+ domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
+ &acpi_irq_gc_ops, priv);
+ else
+ domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
&irq_generic_chip_ops, priv);
if (!domain) {
pr_err("loongson-liointc: cannot add IRQ domain\n");
- err = -EINVAL;
- goto out_iounmap_isr;
+ goto out_iounmap;
}
- err = irq_alloc_domain_generic_chips(domain, 32, 1,
- node->full_name, handle_level_irq,
- IRQ_NOPROBE, 0, 0);
+ err = irq_alloc_domain_generic_chips(domain, LIOINTC_CHIP_IRQ, 1,
+ (node ? node->full_name : "LIOINTC"),
+ handle_level_irq, 0, IRQ_NOPROBE, 0);
if (err) {
pr_err("loongson-liointc: unable to register IRQ domain\n");
goto out_free_domain;
@@ -299,24 +288,112 @@ static int __init liointc_of_init(struct device_node *node,
liointc_chained_handle_irq, &priv->handler[i]);
}
+ liointc_handle = domain_handle;
return 0;
out_free_domain:
irq_domain_remove(domain);
-out_iounmap_isr:
- for (i = 0; i < LIOINTC_NUM_CORES; i++) {
- if (!priv->core_isr[i])
- continue;
- iounmap(priv->core_isr[i]);
- }
-out_iounmap_base:
+out_iounmap:
iounmap(base);
out_free_priv:
kfree(priv);
- return err;
+ return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+
+static int __init liointc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ bool have_parent = FALSE;
+ int sz, i, index, revision, err = 0;
+ struct resource res;
+
+ if (!of_device_is_compatible(node, "loongson,liointc-2.0")) {
+ index = 0;
+ revision = 1;
+ } else {
+ index = of_property_match_string(node, "reg-names", "main");
+ revision = 2;
+ }
+
+ if (of_address_to_resource(node, index, &res))
+ return -EINVAL;
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
+ if (parent_irq[i] > 0)
+ have_parent = TRUE;
+ }
+ if (!have_parent)
+ return -ENODEV;
+
+ sz = of_property_read_variable_u32_array(node,
+ "loongson,parent_int_map",
+ &parent_int_map[0],
+ LIOINTC_NUM_PARENT,
+ LIOINTC_NUM_PARENT);
+ if (sz < 4) {
+ pr_err("loongson-liointc: No parent_int_map\n");
+ return -ENODEV;
+ }
+
+ err = liointc_init(res.start, resource_size(&res),
+ revision, of_node_to_fwnode(node), node);
+ if (err < 0)
+ return err;
+
+ return 0;
}
IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+static int __init
+htintc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_ht_pic *htintc_entry = (struct acpi_madt_ht_pic *)header;
+ struct irq_domain *parent = irq_find_matching_fwnode(liointc_handle, DOMAIN_BUS_ANY);
+
+ return htvec_acpi_init(parent, htintc_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_HT_PIC,
+ htintc_parse_madt, 0);
+ return 0;
+}
+int __init liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_lio_pic *acpi_liointc)
+{
+ int ret;
+ struct fwnode_handle *domain_handle;
+
+ if (!acpi_liointc)
+ return -EINVAL;
+
+ parent_int_map[0] = acpi_liointc->cascade_map[0];
+ parent_int_map[1] = acpi_liointc->cascade_map[1];
+
+ parent_irq[0] = irq_create_mapping(parent, acpi_liointc->cascade[0]);
+ parent_irq[1] = irq_create_mapping(parent, acpi_liointc->cascade[1]);
+
+ domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_liointc);
+ if (!domain_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ return -ENOMEM;
+ }
+ ret = liointc_init(acpi_liointc->address, acpi_liointc->size,
+ 1, domain_handle, NULL);
+ if (ret == 0)
+ acpi_cascade_irqdomain_init();
+
+ return ret;
+}
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 10/13] irqchip: Add Loongson Extended I/O interrupt controller support
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (8 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 09/13] irqchip/loongson-liointc: " Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 11/13] irqchip: Add LoongArch CPU " Jianmin Lv
` (2 subsequent siblings)
12 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
EIOINTC stands for "Extended I/O Interrupts" that described in Section
11.2 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.
Loongson-3A5000 has 4 cores per NUMA node, and each NUMA node has an
EIOINTC; while Loongson-3C5000 has 16 cores per NUMA node, and each NUMA
node has 4 EIOINTCs. In other words, 16 cores of one NUMA node in
Loongson-3C5000 are organized in 4 groups, each group connects to an
EIOINTC. We call the "group" here as an EIOINTC node, so each EIOINTC
node always includes 4 cores (both in Loongson-3A5000 and Loongson-
3C5000).
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 11 +-
drivers/irqchip/Kconfig | 10 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-eiointc.c | 375 +++++++++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
5 files changed, 388 insertions(+), 10 deletions(-)
create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index fbd2bc9..021b8b5 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -87,15 +87,6 @@ struct acpi_vector_group {
extern int find_pch_pic(u32 gsi);
extern int eiointc_get_node(int id);
-static inline void eiointc_enable(void)
-{
- uint64_t misc;
-
- misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
- misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
- iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
-}
-
struct acpi_madt_lio_pic;
struct acpi_madt_eio_pic;
struct acpi_madt_ht_pic;
@@ -107,7 +98,7 @@ static inline void eiointc_enable(void)
int liointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lio_pic *acpi_liointc);
-struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
+int eiointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_eio_pic *acpi_eiointc);
int htvec_acpi_init(struct irq_domain *parent,
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c1d527f..e918579 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -555,6 +555,16 @@ config LOONGSON_LIOINTC
help
Support for the Loongson Local I/O Interrupt Controller.
+config LOONGSON_EIOINTC
+ bool "Loongson Extend I/O Interrupt Controller"
+ depends on LOONGARCH
+ depends on MACH_LOONGSON64
+ default MACH_LOONGSON64
+ select IRQ_DOMAIN_HIERARCHY
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson3 Extend I/O Interrupt Vector Controller.
+
config LOONGSON_HTPIC
bool "Loongson3 HyperTransport PIC Controller"
depends on MACH_LOONGSON64 && MIPS
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 242b8b3..0cfd4f0 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -104,6 +104,7 @@ obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o
obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
+obj-$(CONFIG_LOONGSON_EIOINTC) += irq-loongson-eiointc.o
obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
new file mode 100644
index 0000000..e347af5
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-eiointc.c
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson Extend I/O Interrupt Controller support
+ *
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#define pr_fmt(fmt) "eiointc: " fmt
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#define EIOINTC_REG_NODEMAP 0x14a0
+#define EIOINTC_REG_IPMAP 0x14c0
+#define EIOINTC_REG_ENABLE 0x1600
+#define EIOINTC_REG_BOUNCE 0x1680
+#define EIOINTC_REG_ISR 0x1800
+#define EIOINTC_REG_ROUTE 0x1c00
+
+#define VEC_REG_COUNT 4
+#define VEC_COUNT_PER_REG 64
+#define VEC_COUNT (VEC_REG_COUNT * VEC_COUNT_PER_REG)
+#define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
+#define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
+#define EIOINTC_ALL_ENABLE 0xffffffff
+
+#define MAX_EIO_NODES (NR_CPUS / CORES_PER_EIO_NODE)
+
+static int nr_pics;
+
+struct eiointc_priv {
+ u32 node;
+ nodemask_t node_map;
+ cpumask_t cpuspan_map;
+ struct fwnode_handle *domain_handle;
+ struct irq_domain *eiointc_domain;
+};
+
+static struct eiointc_priv *eiointc_priv[2];
+
+static void eiointc_enable(void)
+{
+ uint64_t misc;
+
+ misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
+ misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
+ iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
+}
+
+static int cpu_to_eio_node(int cpu)
+{
+ return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
+}
+
+static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
+{
+ int i, node, cpu_node, route_node;
+ unsigned char coremap[MAX_EIO_NODES];
+ uint32_t pos_off, data, data_byte, data_mask;
+
+ pos_off = pos & ~3;
+ data_byte = pos & 3;
+ data_mask = ~BIT_MASK(data_byte) & 0xf;
+
+ memset(coremap, 0, sizeof(unsigned char) * MAX_EIO_NODES);
+
+ /* Calculate node and coremap of target irq */
+ cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
+ coremap[cpu_node] |= BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
+
+ for_each_online_cpu(i) {
+ node = cpu_to_eio_node(i);
+ if (!node_isset(node, *node_map))
+ continue;
+
+ /* EIO node 0 is in charge of inter-node interrupt dispatch */
+ route_node = (node == mnode) ? cpu_node : node;
+ data = ((coremap[node] | (route_node << 4)) << (data_byte * 8));
+ csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
+ }
+}
+
+static DEFINE_RAW_SPINLOCK(affinity_lock);
+
+static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
+{
+ unsigned int cpu;
+ unsigned long flags;
+ uint32_t vector, regaddr;
+ struct cpumask intersect_affinity;
+ struct eiointc_priv *priv = d->domain->host_data;
+
+ if (!IS_ENABLED(CONFIG_SMP))
+ return -EPERM;
+
+ raw_spin_lock_irqsave(&affinity_lock, flags);
+
+ cpumask_and(&intersect_affinity, affinity, cpu_online_mask);
+ cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map);
+
+ if (cpumask_empty(&intersect_affinity)) {
+ raw_spin_unlock_irqrestore(&affinity_lock, flags);
+ return -EINVAL;
+ }
+ cpu = cpumask_first(&intersect_affinity);
+
+ if (!d->parent_data)
+ vector = d->hwirq;
+ else
+ vector = d->parent_data->hwirq;
+
+ regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
+
+ /* Mask target vector */
+ csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), 0x0, 0);
+ /* Set route for target vector */
+ eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
+ /* Unmask target vector */
+ csr_any_send(regaddr, EIOINTC_ALL_ENABLE, 0x0, 0);
+
+ irq_data_update_effective_affinity(d, cpumask_of(cpu));
+
+ raw_spin_unlock_irqrestore(&affinity_lock, flags);
+
+ return IRQ_SET_MASK_OK;
+}
+
+static int eiointc_index(int node)
+{
+ int i;
+
+ for (i = 0; i < nr_pics; i++) {
+ if (node_isset(node, eiointc_priv[i]->node_map))
+ return i;
+ }
+
+ return -1;
+}
+
+static int eiointc_router_init(unsigned int cpu)
+{
+ int i, bit;
+ uint32_t data;
+ uint32_t node = cpu_to_eio_node(cpu);
+ uint32_t index = eiointc_index(node);
+
+ if (index < 0) {
+ pr_err("Error: invalid nodemap!\n");
+ return -1;
+ }
+
+ if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
+ eiointc_enable();
+
+ for (i = 0; i < VEC_COUNT / 32; i++) {
+ data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
+ iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
+ }
+
+ for (i = 0; i < VEC_COUNT / 32 / 4; i++) {
+ bit = BIT(1 + index); /* Route to IP[1 + index] */
+ data = bit | (bit << 8) | (bit << 16) | (bit << 24);
+ iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
+ }
+
+ for (i = 0; i < VEC_COUNT / 4; i++) {
+ /* Route to Node-0 Core-0 */
+ if (index == 0)
+ bit = BIT(cpu_logical_map(0));
+ else
+ bit = (eiointc_priv[index]->node << 4) | 1;
+
+ data = bit | (bit << 8) | (bit << 16) | (bit << 24);
+ iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
+ }
+
+ for (i = 0; i < VEC_COUNT / 32; i++) {
+ data = 0xffffffff;
+ iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
+ iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
+ }
+ }
+
+ return 0;
+}
+
+static void eiointc_irq_dispatch(struct irq_desc *desc)
+{
+ int i;
+ u64 pending;
+ bool handled = false;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
+
+ chained_irq_enter(chip, desc);
+
+ for (i = 0; i < VEC_REG_COUNT; i++) {
+ pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
+ iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
+ while (pending) {
+ int bit = __ffs(pending);
+ int irq = bit + VEC_COUNT_PER_REG * i;
+
+ generic_handle_domain_irq(priv->eiointc_domain, irq);
+ pending &= ~BIT(bit);
+ handled = true;
+ }
+ }
+
+ if (!handled)
+ spurious_interrupt();
+
+ chained_irq_exit(chip, desc);
+}
+
+static void eiointc_ack_irq(struct irq_data *d)
+{
+ if (d->parent_data)
+ irq_chip_ack_parent(d);
+}
+
+static void eiointc_mask_irq(struct irq_data *d)
+{
+ if (d->parent_data)
+ irq_chip_mask_parent(d);
+}
+
+static void eiointc_unmask_irq(struct irq_data *d)
+{
+ if (d->parent_data)
+ irq_chip_unmask_parent(d);
+}
+
+static struct irq_chip eiointc_irq_chip = {
+ .name = "EIOINTC",
+ .irq_ack = eiointc_ack_irq,
+ .irq_mask = eiointc_mask_irq,
+ .irq_unmask = eiointc_unmask_irq,
+ .irq_set_affinity = eiointc_set_irq_affinity,
+};
+
+static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int ret;
+ unsigned int i, type;
+ unsigned long hwirq = 0;
+ struct eiointc *priv = domain->host_data;
+
+ ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++) {
+ irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
+ priv, handle_edge_irq, NULL, NULL);
+ }
+
+ return 0;
+}
+
+static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ int i;
+
+ for (i = 0; i < nr_irqs; i++) {
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
+
+ irq_set_handler(virq + i, NULL);
+ irq_domain_reset_irq_data(d);
+ }
+}
+
+static const struct irq_domain_ops eiointc_domain_ops = {
+ .translate = irq_domain_translate_onecell,
+ .alloc = eiointc_domain_alloc,
+ .free = eiointc_domain_free,
+};
+
+static void acpi_set_msi_parent(int node, struct irq_domain *parent)
+{
+ int i;
+
+ if (cpu_has_flatmode)
+ node = cpu_to_node(node * CORES_PER_EIO_NODE);
+
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ if (node == msi_group[i].node) {
+ msi_group[i].parent = parent;
+ return;
+ }
+ }
+}
+
+static void acpi_set_pch_parent(int node, struct irq_domain *parent)
+{
+ int i;
+
+ if (cpu_has_flatmode)
+ node = cpu_to_node(node * CORES_PER_EIO_NODE);
+
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ pch_group[i].parent = parent;
+ pch_group[i].node = node;
+ }
+}
+
+int __init eiointc_acpi_init(struct irq_domain *parent,
+ struct acpi_madt_eio_pic *acpi_eiointc)
+{
+ int i, parent_irq;
+ unsigned long node_map;
+ struct eiointc_priv *priv;
+
+ if (!acpi_eiointc)
+ return -EINVAL;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_eiointc);
+ if (!priv->domain_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ goto out_free_priv;
+ }
+
+ priv->node = acpi_eiointc->node;
+ node_map = acpi_eiointc->node_map ? : -1ULL;
+
+ for_each_possible_cpu(i) {
+ if (node_map & (1ULL << cpu_to_eio_node(i))) {
+ node_set(cpu_to_eio_node(i), priv->node_map);
+ cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i));
+ }
+ }
+
+ /* Setup IRQ domain */
+ priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT,
+ &eiointc_domain_ops, priv);
+ if (!priv->eiointc_domain) {
+ pr_err("loongson-eiointc: cannot add IRQ domain\n");
+ goto out_free_priv;
+ }
+
+ eiointc_priv[nr_pics++] = priv;
+
+ eiointc_router_init(0);
+
+ parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
+ irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
+
+ cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING,
+ "irqchip/loongarch/intc:starting",
+ eiointc_router_init, NULL);
+
+ acpi_set_msi_parent(acpi_eiointc->node, priv->eiointc_domain);
+ acpi_set_pch_parent(acpi_eiointc->node, priv->eiointc_domain);
+ return 0;
+
+out_free_priv:
+ priv->domain_handle = NULL;
+ kfree(priv);
+
+ return -ENOMEM;
+}
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 19f0dbf..de662f3 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -151,6 +151,7 @@ enum cpuhp_state {
CPUHP_AP_IRQ_BCM2836_STARTING,
CPUHP_AP_IRQ_MIPS_GIC_STARTING,
CPUHP_AP_IRQ_RISCV_STARTING,
+ CPUHP_AP_IRQ_LOONGARCH_STARTING,
CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
CPUHP_AP_ARM_MVEBU_COHERENCY,
CPUHP_AP_MICROCODE_LOADER,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 11/13] irqchip: Add LoongArch CPU interrupt controller support
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (9 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 10/13] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 12/13] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 13/13] LoongArch: Fix irq number for timer and ipi Jianmin Lv
12 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
controller that described in Section 7.4 of "LoongArch Reference Manual,
Vol 1". For more information please refer Documentation/loongarch/irq-
chip-model.rst.
LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
(Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
bits, so we define get_xxx_irq() for them.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 4 --
arch/loongarch/kernel/irq.c | 1 -
drivers/irqchip/Kconfig | 10 +++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongarch-cpu.c | 131 ++++++++++++++++++++++++++++++++++++
5 files changed, 142 insertions(+), 5 deletions(-)
create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 021b8b5..fe61288 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -94,13 +94,10 @@ struct acpi_vector_group {
struct acpi_madt_msi_pic;
struct acpi_madt_lpc_pic;
-struct irq_domain *loongarch_cpu_irq_init(void);
-
int liointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lio_pic *acpi_liointc);
int eiointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_eio_pic *acpi_eiointc);
-
int htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
int pch_lpc_acpi_init(struct irq_domain *parent,
@@ -116,7 +113,6 @@ int pch_lpc_acpi_init(struct irq_domain *parent,
extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS];
extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
-extern struct irq_domain *cpu_domain;
extern struct fwnode_handle *liointc_handle;
extern struct fwnode_handle *pch_lpc_handle;
extern struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 5695826..bb53ede 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -25,7 +25,6 @@
DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
EXPORT_PER_CPU_SYMBOL(irq_stat);
-struct irq_domain *cpu_domain;
struct acpi_vector_group pch_group[MAX_IO_PICS];
struct acpi_vector_group msi_group[MAX_IO_PICS];
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e918579..ebfa2cd 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -546,6 +546,16 @@ config EXYNOS_IRQ_COMBINER
Say yes here to add support for the IRQ combiner devices embedded
in Samsung Exynos chips.
+config IRQ_LOONGARCH_CPU
+ bool
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_EFFECTIVE_AFF_MASK
+ help
+ Support for the LoongArch CPU Interrupt Controller. For details of
+ irq chip hierarchy on LoongArch platforms please read the document
+ Documentation/loongarch/irq-chip-model.rst.
+
config LOONGSON_LIOINTC
bool "Loongson Local I/O Interrupt Controller"
depends on MACH_LOONGSON64
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 0cfd4f0..e559007 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -103,6 +103,7 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o
+obj-$(CONFIG_IRQ_LOONGARCH_CPU) += irq-loongarch-cpu.o
obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
obj-$(CONFIG_LOONGSON_EIOINTC) += irq-loongson-eiointc.o
obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
new file mode 100644
index 0000000..f2dfbcb
--- /dev/null
+++ b/drivers/irqchip/irq-loongarch-cpu.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+
+#include <asm/loongarch.h>
+#include <asm/setup.h>
+
+static struct irq_domain *irq_domain;
+
+static void mask_loongarch_irq(struct irq_data *d)
+{
+ clear_csr_ecfg(ECFGF(d->hwirq));
+}
+
+static void unmask_loongarch_irq(struct irq_data *d)
+{
+ set_csr_ecfg(ECFGF(d->hwirq));
+}
+
+static struct irq_chip cpu_irq_controller = {
+ .name = "CPUINTC",
+ .irq_mask = mask_loongarch_irq,
+ .irq_unmask = unmask_loongarch_irq,
+};
+
+static void handle_cpu_irq(struct pt_regs *regs)
+{
+ int hwirq;
+ unsigned int estat = read_csr_estat() & CSR_ESTAT_IS;
+
+ while ((hwirq = ffs(estat))) {
+ estat &= ~BIT(hwirq - 1);
+ generic_handle_domain_irq(irq_domain, hwirq - 1);
+ }
+}
+
+int get_ipi_irq(void)
+{
+ return irq_create_mapping(irq_domain, EXCCODE_IPI - EXCCODE_INT_START);
+}
+
+int get_pmc_irq(void)
+{
+ return irq_create_mapping(irq_domain, EXCCODE_PMC - EXCCODE_INT_START);
+}
+
+int get_timer_irq(void)
+{
+ return irq_create_mapping(irq_domain, EXCCODE_TIMER - EXCCODE_INT_START);
+}
+
+static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ irq_set_noprobe(irq);
+ irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = {
+ .map = loongarch_cpu_intc_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+struct irq_domain * __init loongarch_cpu_irq_init(void)
+{
+ struct fwnode_handle *domain_handle;
+
+ /* Mask interrupts. */
+ clear_csr_ecfg(ECFG0_IM);
+ clear_csr_estat(ESTATF_IP);
+
+ domain_handle = irq_domain_alloc_fwnode(NULL);
+ irq_domain = irq_domain_create_linear(domain_handle, EXCCODE_INT_NUM,
+ &loongarch_cpu_intc_irq_domain_ops, NULL);
+
+ if (!irq_domain)
+ panic("Failed to add irqdomain for LoongArch CPU");
+
+ set_handle_irq(&handle_cpu_irq);
+
+ return irq_domain;
+}
+
+static int __init
+liointc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header;
+
+ return liointc_acpi_init(irq_domain, liointc_entry);
+}
+
+static int __init
+eiointc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header;
+
+ return eiointc_acpi_init(irq_domain, eiointc_entry);
+}
+static int __init acpi_cascade_irqdomain_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC,
+ liointc_parse_madt, 0);
+ acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC,
+ eiointc_parse_madt, 0);
+ return 0;
+}
+static int __init coreintc_acpi_init_v1(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ if (irq_domain)
+ return 0;
+
+ loongarch_cpu_irq_init();
+ acpi_cascade_irqdomain_init();
+ return 0;
+}
+IRQCHIP_ACPI_DECLARE(coreintc_v1, ACPI_MADT_TYPE_CORE_PIC,
+ NULL, ACPI_MADT_CORE_PIC_VERSION_V1,
+ coreintc_acpi_init_v1);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 12/13] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (10 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 11/13] irqchip: Add LoongArch CPU " Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 13/13] LoongArch: Fix irq number for timer and ipi Jianmin Lv
12 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
For LoongArch, ACPI_IRQ_MODEL_LPIC is introduced, and then the
callback acpi_get_gsi_domain_id is implemented.
The acpi_get_gsi_domain_id callback returns related fwnode handle
of irqdomain for different GSI range.
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/acpi/bus.c | 3 +++
drivers/irqchip/irq-loongarch-cpu.c | 37 +++++++++++++++++++++++++++++++++++++
include/linux/acpi.h | 1 +
3 files changed, 41 insertions(+)
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 86fa61a..63fbf00 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -1145,6 +1145,9 @@ static int __init acpi_bus_init_irq(void)
case ACPI_IRQ_MODEL_PLATFORM:
message = "platform specific model";
break;
+ case ACPI_IRQ_MODEL_LPIC:
+ message = "LPIC";
+ break;
default:
pr_info("Unknown interrupt routing model\n");
return -ENODEV;
diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
index f2dfbcb..eee21c9 100644
--- a/drivers/irqchip/irq-loongarch-cpu.c
+++ b/drivers/irqchip/irq-loongarch-cpu.c
@@ -15,6 +15,41 @@
static struct irq_domain *irq_domain;
+static int lpic_gsi_to_irq(u32 gsi)
+{
+ /* Only pch irqdomain transferring is required for LoongArch. */
+ if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
+ return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
+ return -1;
+}
+
+struct fwnode_handle *lpic_get_gsi_domain_id(u32 gsi)
+{
+ int id;
+ struct fwnode_handle *domain_handle = NULL;
+
+ switch (gsi) {
+ case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
+ if (liointc_handle)
+ domain_handle = liointc_handle;
+ break;
+
+ case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
+ if (pch_lpc_handle)
+ domain_handle = pch_lpc_handle;
+ break;
+
+ case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
+ id = find_pch_pic(gsi);
+ if (id >= 0 && pch_pic_handle[id])
+ domain_handle = pch_pic_handle[id];
+
+ break;
+ }
+
+ return domain_handle;
+}
+
static void mask_loongarch_irq(struct irq_data *d)
{
clear_csr_ecfg(ECFGF(d->hwirq));
@@ -87,6 +122,8 @@ struct irq_domain * __init loongarch_cpu_irq_init(void)
panic("Failed to add irqdomain for LoongArch CPU");
set_handle_irq(&handle_cpu_irq);
+ acpi_set_irq_model(ACPI_IRQ_MODEL_LPIC, lpic_get_gsi_domain_id);
+ acpi_set_gsi_to_irq_fallback(lpic_gsi_to_irq);
return irq_domain;
}
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 71d3719..1bec0a3 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -105,6 +105,7 @@ enum acpi_irq_model_id {
ACPI_IRQ_MODEL_IOSAPIC,
ACPI_IRQ_MODEL_PLATFORM,
ACPI_IRQ_MODEL_GIC,
+ ACPI_IRQ_MODEL_LPIC,
ACPI_IRQ_MODEL_COUNT
};
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V13 13/13] LoongArch: Fix irq number for timer and ipi
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (11 preceding siblings ...)
2022-06-27 11:39 ` [PATCH V13 12/13] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
@ 2022-06-27 11:39 ` Jianmin Lv
12 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-27 11:39 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
After supporting LoongArch CPUINTC controller driver, the
irq number of interrupt source from CPUINTC is needed to transfer
from CPUINTC irqdomain, so use api of CPUINTC to transfer it.
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
arch/loongarch/kernel/irq.c | 2 +-
arch/loongarch/kernel/time.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index bb53ede..f342307f 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -96,7 +96,7 @@ void __init init_IRQ(void)
init_msi_parent_group();
irqchip_init();
#ifdef CONFIG_SMP
- ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
+ ipi_irq = get_ipi_irq();
irq_set_percpu_devid(ipi_irq);
r = request_percpu_irq(ipi_irq, loongson3_ipi_interrupt, "IPI", &ipi_dummy_dev);
if (r < 0)
diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
index fe68238..4a04aa6 100644
--- a/arch/loongarch/kernel/time.c
+++ b/arch/loongarch/kernel/time.c
@@ -132,7 +132,7 @@ int constant_clockevent_init(void)
struct clock_event_device *cd;
static int timer_irq_installed = 0;
- irq = EXCCODE_TIMER - EXCCODE_INT_START;
+ irq = get_timer_irq();
cd = &per_cpu(constant_clockevent_device, cpu);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH V13 01/13] APCI: irq: Add support for multiple GSI domains
2022-06-27 11:39 ` [PATCH V13 01/13] APCI: irq: Add support for multiple GSI domains Jianmin Lv
@ 2022-06-28 12:50 ` Hanjun Guo
0 siblings, 0 replies; 26+ messages in thread
From: Hanjun Guo @ 2022-06-28 12:50 UTC (permalink / raw)
To: Jianmin Lv, Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On 2022/6/27 19:39, Jianmin Lv wrote:
> From: Marc Zyngier <maz@kernel.org>
>
> In an unfortunate departure from the ACPI spec, the LoongArch
> architecture split its GSI space across multiple interrupt
> controllers.
>
> In order to be able to reuse sthe core code and prevent
s/sthe/the
> architectures from reinventing an already square wheel, offer
> the arch code the ability to register a dispatcher function
> that will return the domain fwnode for a given GSI.
>
> The ARM GIC drivers are updated to support this (with a single
> domain, as intended).
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Cc: Hanjun Guo <guohanjun@huawei.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> ---
> drivers/acpi/irq.c | 40 +++++++++++++++++++++++++---------------
> drivers/irqchip/irq-gic-v3.c | 18 ++++++++++++------
> drivers/irqchip/irq-gic.c | 18 ++++++++++++------
> include/linux/acpi.h | 2 +-
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
I tested this patch on a GICv3 based ARM64 server, no
regressions were found,
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Thanks
Hanjun
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 02/13] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
2022-06-27 11:39 ` [PATCH V13 02/13] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
@ 2022-06-28 13:26 ` Hanjun Guo
0 siblings, 0 replies; 26+ messages in thread
From: Hanjun Guo @ 2022-06-28 13:26 UTC (permalink / raw)
To: Jianmin Lv, Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On 2022/6/27 19:39, Jianmin Lv wrote:
> From: Marc Zyngier <maz@kernel.org>
>
> It appears that the generic version of acpi_gsi_to_irq() doesn't
> fallback to establishing a mapping if there is no pre-existing
> one while the x86 version does.
>
> While arm64 seems unaffected by it, LoongArch is relying on the x86
> behaviour. In an effort to prevent new architectures from reinventing
> the proverbial wheel, provide an optional callback that the arch code
> can set to restore the x86 behaviour.
>
> Hopefully we can eventually get rid of this in the future once
> the expected behaviour has been clarified.
>
> Reported-by: Jianmin Lv <lvjianmin@loongson.cn>
Why do we need the Reported-by tag here?
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> ---
> drivers/acpi/irq.c | 18 ++++++++++++++++--
> include/linux/acpi.h | 1 +
> 2 files changed, 17 insertions(+), 2 deletions(-)
The rest is looking good to me,
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Thanks
Hanjun
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 05/13] irqchip: Add Loongson PCH LPC controller support
2022-06-27 11:39 ` [PATCH V13 05/13] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
@ 2022-06-29 10:58 ` Marc Zyngier
2022-06-30 4:40 ` Jianmin Lv
0 siblings, 1 reply; 26+ messages in thread
From: Marc Zyngier @ 2022-06-29 10:58 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On Mon, 27 Jun 2022 12:39:49 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> From: Huacai Chen <chenhuacai@loongson.cn>
>
> PCH-LPC stands for "LPC Interrupts" that described in Section 24.3 of
> "Loongson 7A1000 Bridge User Manual". For more information please refer
> Documentation/loongarch/irq-chip-model.rst.
>
> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
> arch/loongarch/include/asm/irq.h | 4 +-
> arch/loongarch/kernel/irq.c | 1 -
> drivers/irqchip/Kconfig | 8 ++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-loongson-pch-lpc.c | 203 +++++++++++++++++++++++++++++++++
> 5 files changed, 214 insertions(+), 3 deletions(-)
> create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c
>
> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
> index ace3ea6..48c0ce4 100644
> --- a/arch/loongarch/include/asm/irq.h
> +++ b/arch/loongarch/include/asm/irq.h
> @@ -104,7 +104,7 @@ struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
>
> struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
> struct acpi_madt_ht_pic *acpi_htvec);
> -struct irq_domain *pch_lpc_acpi_init(struct irq_domain *parent,
> +int pch_lpc_acpi_init(struct irq_domain *parent,
> struct acpi_madt_lpc_pic *acpi_pchlpc);
> struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
> struct acpi_madt_msi_pic *acpi_pchmsi);
> @@ -121,7 +121,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
>
> extern struct irq_domain *cpu_domain;
> extern struct irq_domain *liointc_domain;
> -extern struct irq_domain *pch_lpc_domain;
> +extern struct fwnode_handle *pch_lpc_handle;
> extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
> extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
>
> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
> index b34b8d7..07d6059 100644
> --- a/arch/loongarch/kernel/irq.c
> +++ b/arch/loongarch/kernel/irq.c
> @@ -27,7 +27,6 @@
>
> struct irq_domain *cpu_domain;
> struct irq_domain *liointc_domain;
> -struct irq_domain *pch_lpc_domain;
> struct irq_domain *pch_msi_domain[MAX_IO_PICS];
> struct irq_domain *pch_pic_domain[MAX_IO_PICS];
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 1f23a6b..c1d527f 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -591,6 +591,14 @@ config LOONGSON_PCH_MSI
> help
> Support for the Loongson PCH MSI Controller.
>
> +config LOONGSON_PCH_LPC
> + bool "Loongson PCH LPC Controller"
> + depends on MACH_LOONGSON64
> + default (MACH_LOONGSON64 && LOONGARCH)
> + select IRQ_DOMAIN_HIERARCHY
> + help
> + Support for the Loongson PCH LPC Controller.
> +
> config MST_IRQ
> bool "MStar Interrupt Controller"
> depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 5b67450..242b8b3 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -108,6 +108,7 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
> obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
> obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
> obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
> +obj-$(CONFIG_LOONGSON_PCH_LPC) += irq-loongson-pch-lpc.o
> obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
> obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o
> obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
> diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
> new file mode 100644
> index 0000000..7e4d89a
> --- /dev/null
> +++ b/drivers/irqchip/irq-loongson-pch-lpc.c
> @@ -0,0 +1,203 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Loongson LPC Interrupt Controller support
> + *
> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
> + */
> +
> +#define pr_fmt(fmt) "lpc: " fmt
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +
> +/* Registers */
> +#define LPC_INT_CTL 0x00
> +#define LPC_INT_ENA 0x04
> +#define LPC_INT_STS 0x08
> +#define LPC_INT_CLR 0x0c
> +#define LPC_INT_POL 0x10
> +#define LPC_COUNT 16
> +
> +struct pch_lpc {
> + void __iomem *base;
> + struct irq_domain *lpc_domain;
> + raw_spinlock_t lpc_lock;
> + u32 saved_reg_ctl;
> + u32 saved_reg_ena;
> + u32 saved_reg_pol;
> +};
> +
> +struct fwnode_handle *pch_lpc_handle;
> +
> +static void ack_lpc_irq(struct irq_data *d)
> +{
> + unsigned long flags;
> + struct pch_lpc *priv = d->domain->host_data;
> +
> + raw_spin_lock_irqsave(&priv->lpc_lock, flags);
> + writel(0x1 << d->hwirq, priv->base + LPC_INT_CLR);
> + raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
> +}
> +static void mask_lpc_irq(struct irq_data *d)
> +{
> + unsigned long flags;
> + struct pch_lpc *priv = d->domain->host_data;
> +
> + raw_spin_lock_irqsave(&priv->lpc_lock, flags);
> + writel(readl(priv->base + LPC_INT_ENA) & (~(0x1 << (d->hwirq))),
> + priv->base + LPC_INT_ENA);
> + raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
> +}
> +
> +static void unmask_lpc_irq(struct irq_data *d)
> +{
> + unsigned long flags;
> + struct pch_lpc *priv = d->domain->host_data;
> +
> + raw_spin_lock_irqsave(&priv->lpc_lock, flags);
> + writel(readl(priv->base + LPC_INT_ENA) | (0x1 << (d->hwirq)),
> + priv->base + LPC_INT_ENA);
> + raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
> +}
> +
> +static int lpc_set_type(struct irq_data *d, unsigned int type)
> +{
> + u32 val;
> + u32 mask = 0x1 << (d->hwirq);
> + struct pch_lpc *priv = d->domain->host_data;
> +
> + if (!(type & IRQ_TYPE_LEVEL_MASK))
> + return 0;
> +
> + val = readl(priv->base + LPC_INT_POL);
> +
> + if (type == IRQ_TYPE_LEVEL_HIGH)
> + val |= mask;
> + else
> + val &= ~mask;
> +
> + writel(val, priv->base + LPC_INT_POL);
> +
> + return 0;
> +}
> +
> +static struct irq_chip pch_lpc_irq_chip = {
Make this const.
> + .name = "PCH LPC",
> + .irq_mask = mask_lpc_irq,
> + .irq_unmask = unmask_lpc_irq,
> + .irq_ack = ack_lpc_irq,
> + .irq_set_type = lpc_set_type,
nit: please use the same format for all callbacks: lpc_irq_OPERATION
(lpc_irq_mask, lpc_irq_set_type...), which makes it much easier to
read.
> + .flags = IRQCHIP_SKIP_SET_WAKE,
> +};
> +
> +static void lpc_irq_dispatch(struct irq_desc *desc)
> +{
> + u32 pending, bit, virq;
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + struct pch_lpc *priv = irq_desc_get_handler_data(desc);
> +
> + chained_irq_enter(chip, desc);
> +
> + pending = readl(priv->base + LPC_INT_ENA);
> + pending &= readl(priv->base + LPC_INT_STS);
> + if (!pending)
> + spurious_interrupt();
> +
> + while (pending) {
> + bit = __ffs(pending);
> + virq = irq_linear_revmap(priv->lpc_domain, bit);
> +
> + generic_handle_irq(bit);
Replace the whole thing with a call to generic_handle_domain_irq(). No
new code should ever have to use generic_handle_irq().
> + pending &= ~BIT(bit);
> + }
> + chained_irq_exit(chip, desc);
> +}
> +
> +static int pch_lpc_map(struct irq_domain *d, unsigned int irq,
> + irq_hw_number_t hw)
> +{
> + irq_set_chip_and_handler(irq, &pch_lpc_irq_chip, handle_level_irq);
> + return 0;
> +}
> +
> +static const struct irq_domain_ops pch_lpc_domain_ops = {
> + .map = pch_lpc_map,
> + .translate = irq_domain_translate_twocell,
> +};
> +
> +static void pch_lpc_reset(struct pch_lpc *priv)
> +{
> + /* Enable the LPC interrupt, bit31: en bit30: edge */
> + writel(0x80000000, priv->base + LPC_INT_CTL);
Please don't hardcode numbers. Add the proper bit definitions.
> + writel(0, priv->base + LPC_INT_ENA);
> + /* Clear all 18-bit interrpt bit */
> + writel(0x3ffff, priv->base + LPC_INT_CLR);
If that's just a mask, then use GENMASK(17, 0) instead.
> +}
> +
> +static int pch_lpc_disabled(struct pch_lpc *priv)
> +{
> + return (readl(priv->base + LPC_INT_ENA) == 0xffffffff) &&
> + (readl(priv->base + LPC_INT_STS) == 0xffffffff);
> +}
> +
> +int __init pch_lpc_acpi_init(struct irq_domain *parent,
> + struct acpi_madt_lpc_pic *acpi_pchlpc)
> +{
> + int parent_irq;
> + struct pch_lpc *priv;
> + struct irq_fwspec fwspec;
> + struct fwnode_handle *irq_handle;
> +
> + if (!acpi_pchlpc)
> + return -EINVAL;
> +
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + raw_spin_lock_init(&priv->lpc_lock);
> +
> + priv->base = ioremap(acpi_pchlpc->address, acpi_pchlpc->size);
> + if (!priv->base)
> + goto free_priv;
> +
> + if (pch_lpc_disabled(priv)) {
> + pr_err("Failed to get LPC status\n");
> + goto iounmap_base;
> + }
> +
> + irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
> + if (!irq_handle) {
> + pr_err("Unable to allocate domain handle\n");
> + goto iounmap_base;
> + }
> +
> + priv->lpc_domain = irq_domain_create_linear(irq_handle, LPC_COUNT,
> + &pch_lpc_domain_ops, priv);
> + if (!priv->lpc_domain) {
> + pr_err("Failed to create IRQ domain\n");
> + goto iounmap_base;
You also need to free the fwnode.
> + }
> + pch_lpc_reset(priv);
> +
> + fwspec.fwnode = parent->fwnode;
> + fwspec.param[0] = acpi_pchlpc->cascade;
> + fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
> + fwspec.param_count = 2;
> + parent_irq = irq_create_fwspec_mapping(&fwspec);
> + irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv);
> +
> + pch_lpc_handle = irq_handle;
> + return 0;
> +
> +iounmap_base:
> + iounmap(priv->base);
> +free_priv:
> + kfree(priv);
> +
> + return -ENOMEM;
> +}
> --
> 1.8.3.1
>
>
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 06/13] irqchip/loongson-pch-pic: Add ACPI init support
2022-06-27 11:39 ` [PATCH V13 06/13] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
@ 2022-06-29 11:20 ` Marc Zyngier
2022-06-30 4:36 ` Jianmin Lv
0 siblings, 1 reply; 26+ messages in thread
From: Marc Zyngier @ 2022-06-29 11:20 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On Mon, 27 Jun 2022 12:39:50 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> From: Huacai Chen <chenhuacai@loongson.cn>
>
> We are preparing to add new Loongson (based on LoongArch, not compatible
> with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
> as its boot protocol, so add ACPI init support.
Drop this paragraph.
>
> PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
> Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
> please refer Documentation/loongarch/irq-chip-model.rst.
>
> For systems with two chipsets, there are two related pch irqdomains,
> each of which has the same node id as its parent irqdomain. So we
> defined a structure to mantain the relation of node and it's parent
> irqdomain.
>
> struct acpi_vector_group {
> int node;
> struct irq_domain *parent;
> };
>
> The parent irqdomain will be set for node id in parent irqdomain driver
> before pch irqdomain is created.
>
> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
> arch/loongarch/include/asm/irq.h | 11 +-
> arch/loongarch/kernel/irq.c | 2 +-
> drivers/irqchip/irq-loongson-pch-pic.c | 200 ++++++++++++++++++++++++++++-----
> 3 files changed, 179 insertions(+), 34 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
> index 48c0ce4..a444dc6 100644
> --- a/arch/loongarch/include/asm/irq.h
> +++ b/arch/loongarch/include/asm/irq.h
> @@ -48,6 +48,12 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
> #define MAX_IO_PICS 2
> #define NR_IRQS (64 + (256 * MAX_IO_PICS))
>
> +struct acpi_vector_group {
> + int node;
> + struct irq_domain *parent;
> +};
> +extern struct acpi_vector_group pch_group[MAX_IO_PICS];
> +
> #define CORES_PER_EIO_NODE 4
>
> #define LOONGSON_CPU_UART0_VEC 10 /* CPU UART0 */
> @@ -108,8 +114,7 @@ int pch_lpc_acpi_init(struct irq_domain *parent,
> struct acpi_madt_lpc_pic *acpi_pchlpc);
> struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
> struct acpi_madt_msi_pic *acpi_pchmsi);
> -struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
> - struct acpi_madt_bio_pic *acpi_pchpic);
> +int find_pch_pic(u32 gsi);
>
> extern struct acpi_madt_lio_pic *acpi_liointc;
> extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
> @@ -123,7 +128,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
> extern struct irq_domain *liointc_domain;
> extern struct fwnode_handle *pch_lpc_handle;
> extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
> -extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
> +extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
>
> extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
>
> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
> index 07d6059..f2115be 100644
> --- a/arch/loongarch/kernel/irq.c
> +++ b/arch/loongarch/kernel/irq.c
> @@ -28,7 +28,7 @@
> struct irq_domain *cpu_domain;
> struct irq_domain *liointc_domain;
> struct irq_domain *pch_msi_domain[MAX_IO_PICS];
> -struct irq_domain *pch_pic_domain[MAX_IO_PICS];
> +struct acpi_vector_group pch_group[MAX_IO_PICS];
>
> /*
> * 'what should we do if we get a hw irq event on an illegal vector'.
> diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
> index a4eb8a2..170a5b9 100644
> --- a/drivers/irqchip/irq-loongson-pch-pic.c
> +++ b/drivers/irqchip/irq-loongson-pch-pic.c
> @@ -33,13 +33,40 @@
> #define PIC_REG_IDX(irq_id) ((irq_id) / PIC_COUNT_PER_REG)
> #define PIC_REG_BIT(irq_id) ((irq_id) % PIC_COUNT_PER_REG)
>
> +static int nr_pics;
> +
> struct pch_pic {
> void __iomem *base;
> struct irq_domain *pic_domain;
> + struct fwnode_handle *domain_handle;
> u32 ht_vec_base;
> raw_spinlock_t pic_lock;
> + u32 gsi_end;
> + u32 gsi_base;
> };
>
> +static struct pch_pic *pch_pic_priv[2];
Why 2? Is that related to MAX_IO_PICS being 2?
> +struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
> +
> +int find_pch_pic(u32 gsi)
> +{
> + int i;
> +
> + /* Find the PCH_PIC that manages this GSI. */
> + for (i = 0; i < MAX_IO_PICS; i++) {
> + struct pch_pic *priv = pch_pic_priv[i];
> +
> + if (!priv)
> + return -1;
> +
> + if (gsi >= priv->gsi_base && gsi <= priv->gsi_end)
> + return i;
> + }
> +
> + pr_err("ERROR: Unable to locate PCH_PIC for GSI %d\n", gsi);
> + return -1;
> +}
> +
> static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)
> {
> u32 reg;
> @@ -139,6 +166,24 @@ static void pch_pic_ack_irq(struct irq_data *d)
> .irq_set_type = pch_pic_set_type,
> };
>
> +static int pch_pic_domain_translate(struct irq_domain *d,
> + struct irq_fwspec *fwspec,
> + unsigned long *hwirq,
> + unsigned int *type)
> +{
> + struct pch_pic *priv = d->host_data;
> + struct device_node *of_node = to_of_node(fwspec->fwnode);
> +
> + if (fwspec->param_count < 1)
> + return -EINVAL;
> + if (of_node)
> + *hwirq += priv->ht_vec_base;
> + else
> + *hwirq = fwspec->param[0] - priv->gsi_base;
> + *type = IRQ_TYPE_NONE;
Have you tested this on MIPS HW? This looks like a regression on the
OF path, as it used irq_domain_translate_twocell().
> +
> + return 0;
> +}
> static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
> unsigned int nr_irqs, void *arg)
> {
> @@ -149,13 +194,13 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
> struct irq_fwspec parent_fwspec;
> struct pch_pic *priv = domain->host_data;
>
> - err = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
> + err = pch_pic_domain_translate(domain, fwspec, &hwirq, &type);
> if (err)
> return err;
>
> parent_fwspec.fwnode = domain->parent->fwnode;
> parent_fwspec.param_count = 1;
> - parent_fwspec.param[0] = hwirq + priv->ht_vec_base;
> + parent_fwspec.param[0] = hwirq;
>
> err = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
> if (err)
> @@ -170,7 +215,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
> }
>
> static const struct irq_domain_ops pch_pic_domain_ops = {
> - .translate = irq_domain_translate_twocell,
> + .translate = pch_pic_domain_translate,
> .alloc = pch_pic_alloc,
> .free = irq_domain_free_irqs_parent,
> };
> @@ -180,7 +225,7 @@ static void pch_pic_reset(struct pch_pic *priv)
> int i;
>
> for (i = 0; i < PIC_COUNT; i++) {
> - /* Write vectored ID */
> + /* Write vector ID */
> writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i));
> /* Hardcode route to HT0 Lo */
> writeb(1, priv->base + PCH_INT_ROUTE(i));
> @@ -198,50 +243,41 @@ static void pch_pic_reset(struct pch_pic *priv)
> }
> }
>
> -static int pch_pic_of_init(struct device_node *node,
> - struct device_node *parent)
> +static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base,
> + struct irq_domain *parent_domain, struct fwnode_handle *domain_handle,
> + u32 gsi_base)
> {
> + int vec_count;
> struct pch_pic *priv;
> - struct irq_domain *parent_domain;
> - int err;
>
> priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> if (!priv)
> return -ENOMEM;
>
> raw_spin_lock_init(&priv->pic_lock);
> - priv->base = of_iomap(node, 0);
> - if (!priv->base) {
> - err = -ENOMEM;
> + priv->base = ioremap(addr, size);
> + if (!priv->base)
> goto free_priv;
> - }
>
> - parent_domain = irq_find_host(parent);
> - if (!parent_domain) {
> - pr_err("Failed to find the parent domain\n");
> - err = -ENXIO;
> - goto iounmap_base;
> - }
> + priv->domain_handle = domain_handle;
>
> - if (of_property_read_u32(node, "loongson,pic-base-vec",
> - &priv->ht_vec_base)) {
> - pr_err("Failed to determine pic-base-vec\n");
> - err = -EINVAL;
> - goto iounmap_base;
> - }
> + priv->ht_vec_base = vec_base;
Why isn't this pre-filled on the OF path as it isn't relevant to ACPI?
> + vec_count = ((readq(priv->base) >> 48) & 0xff) + 1;
Is that valid on the old HW?
> + priv->gsi_base = gsi_base;
Why isn't this pre-filled on the ACPI path as it isn't relevant to OF?
> + priv->gsi_end = gsi_base + vec_count - 1;
I don't think this needs to be ACPI specific. Just track the vector
count, which applies to both ACPI and DT.
>
> priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0,
> - PIC_COUNT,
> - of_node_to_fwnode(node),
> - &pch_pic_domain_ops,
> - priv);
> + vec_count, priv->domain_handle,
> + &pch_pic_domain_ops, priv);
> +
> if (!priv->pic_domain) {
> pr_err("Failed to create IRQ domain\n");
> - err = -ENOMEM;
> goto iounmap_base;
> }
>
> pch_pic_reset(priv);
> + pch_pic_handle[nr_pics] = domain_handle;
> + pch_pic_priv[nr_pics++] = priv;
>
> return 0;
>
> @@ -250,7 +286,111 @@ static int pch_pic_of_init(struct device_node *node,
> free_priv:
> kfree(priv);
>
> - return err;
> + return -EINVAL;
> +}
> +
> +#ifdef CONFIG_OF
> +
> +static int pch_pic_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + int err, vec_base;
> + struct resource res;
> + struct irq_domain *parent_domain;
> +
> + if (of_address_to_resource(node, 0, &res))
> + return -EINVAL;
> +
> + parent_domain = irq_find_host(parent);
> + if (!parent_domain) {
> + pr_err("Failed to find the parent domain\n");
> + return -ENXIO;
> + }
> +
> + if (of_property_read_u32(node, "loongson,pic-base-vec", &vec_base)) {
> + pr_err("Failed to determine pic-base-vec\n");
> + return -EINVAL;
> + }
> +
> + err = pch_pic_init(res.start, resource_size(&res), vec_base,
> + parent_domain, of_node_to_fwnode(node), 0);
> + if (err < 0)
> + return err;
> +
> + return 0;
> }
>
> IRQCHIP_DECLARE(pch_pic, "loongson,pch-pic-1.0", pch_pic_of_init);
> +
> +#endif
> +
> +#ifdef CONFIG_ACPI
> +static int __init
> +lpcintc_parse_madt(union acpi_subtable_headers *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_lpc_pic *lpcintc_entry = (struct acpi_madt_lpc_pic *)header;
> +
> + return pch_lpc_acpi_init(pch_pic_priv[0]->pic_domain, lpcintc_entry);
> +}
> +
> +static int __init acpi_cascade_irqdomain_init(void)
> +{
> + acpi_table_parse_madt(ACPI_MADT_TYPE_LPC_PIC,
> + lpcintc_parse_madt, 0);
> + return 0;
> +}
Missing blank line between functions
> +int __init pch_pic_init_irqdomain(struct irq_domain *parent,
> + struct acpi_madt_bio_pic *acpi_pchpic)
> +{
> + int ret, vec_base;
> + struct fwnode_handle *domain_handle;
> +
> + if (!acpi_pchpic)
> + return -EINVAL;
> +
> + vec_base = acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ;
> +
> + domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchpic);
> + if (!domain_handle) {
> + pr_err("Unable to allocate domain handle\n");
> + return -ENOMEM;
> + }
> +
> + ret = pch_pic_init(acpi_pchpic->address, acpi_pchpic->size,
> + vec_base, parent, domain_handle, acpi_pchpic->gsi_base);
> + if (ret == 0 && acpi_pchpic->id == 0)
> + acpi_cascade_irqdomain_init();
> +
> + return ret;
> +}
> +
> +struct irq_domain *acpi_get_pch_parent(int node)
> +{
> + int i;
> +
> + for (i = 0; i < MAX_IO_PICS; i++) {
> + if (node == pch_group[i].node)
> + return pch_group[i].parent;
> + }
> + return NULL;
> +}
> +
> +static int __init pchintc_parse_madt(union acpi_subtable_headers *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_bio_pic *pch_pic_entry = (struct acpi_madt_bio_pic *)header;
> +
> + return pch_pic_init_irqdomain(acpi_get_pch_parent((pch_pic_entry->address >> 44) & 0xf),
> + pch_pic_entry);
> +}
> +
> +static int __init pch_pic_acpi_init(void)
> +{
> + acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
Where is this defined? It only appears in the documentation, and
nowhere else...
> + pchintc_parse_madt, 0);
> +
> + return 0;
> +}
> +early_initcall(pch_pic_acpi_init);
Why can't you use IRQCHIP_ACPI_DECLARE here? This is terribly fragile,
and will eventually break. I really don't want to rely on this.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 09/13] irqchip/loongson-liointc: Add ACPI init support
2022-06-27 11:39 ` [PATCH V13 09/13] irqchip/loongson-liointc: " Jianmin Lv
@ 2022-06-29 13:13 ` Marc Zyngier
2022-06-30 2:52 ` Jianmin Lv
0 siblings, 1 reply; 26+ messages in thread
From: Marc Zyngier @ 2022-06-29 13:13 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On Mon, 27 Jun 2022 12:39:53 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> From: Huacai Chen <chenhuacai@loongson.cn>
>
> We are preparing to add new Loongson (based on LoongArch, not compatible
> with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
> as its boot protocol, so add ACPI init support.
>
> LIOINTC stands for "Legacy I/O Interrupts" that described in Section
> 11.1 of "Loongson 3A5000 Processor Reference Manual". For more
> information please refer Documentation/loongarch/irq-chip-model.rst.
This is what happens with this series while compiling for MIPS:
drivers/irqchip/irq-loongson-liointc.c: In function ‘liointc_domain_xlate’:
drivers/irqchip/irq-loongson-liointc.c:170:28: error: ‘GSI_MIN_CPU_IRQ’ undeclared (first use in this function)
170 | *out_hwirq = intspec[0] - GSI_MIN_CPU_IRQ;
| ^~~~~~~~~~~~~~~
I haven't bothered reviewing more patches, as this is a waste of my
time.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 07/13] irqchip/loongson-pch-msi: Add ACPI init support
2022-06-27 11:39 ` [PATCH V13 07/13] irqchip/loongson-pch-msi: " Jianmin Lv
@ 2022-06-29 13:15 ` Marc Zyngier
2022-06-30 2:51 ` Jianmin Lv
0 siblings, 1 reply; 26+ messages in thread
From: Marc Zyngier @ 2022-06-29 13:15 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On Mon, 27 Jun 2022 12:39:51 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> From: Huacai Chen <chenhuacai@loongson.cn>
>
> We are preparing to add new Loongson (based on LoongArch, not compatible
> with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
> as its boot protocol, so add ACPI init support.
Same rant about the content-less paragraph, which I asked you to drop
a few version ago.
>
> PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
> Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
> please refer Documentation/loongarch/irq-chip-model.rst.
>
> For systems with two chipsets, there are two related msi irqdomains,
> each of which has the same node id as its parent irqdomain. So we
> use a structure to mantain the relation of node and it's parent
> irqdomain as pch irqdomin, and add a pci_segment field to it for
> matching the pci segment of a pci device when setting msi irqdomain
> for the device.
>
> struct acpi_vector_group {
> int node;
> int pci_segment;
> struct irq_domain *parent;
> };
>
> The field 'pci_segment' and 'node' are initialized from MCFG, and
> the parent irqdomain will set field 'parent' by matching same
> 'node'.
>
> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
> arch/loongarch/include/asm/irq.h | 7 +-
> arch/loongarch/kernel/irq.c | 30 ++++++-
> drivers/irqchip/irq-loongson-pch-msi.c | 147 +++++++++++++++++++++++----------
> 3 files changed, 138 insertions(+), 46 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
> index a444dc6..367aa44 100644
> --- a/arch/loongarch/include/asm/irq.h
> +++ b/arch/loongarch/include/asm/irq.h
> @@ -50,9 +50,11 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
>
> struct acpi_vector_group {
> int node;
> + int pci_segment;
> struct irq_domain *parent;
> };
> extern struct acpi_vector_group pch_group[MAX_IO_PICS];
> +extern struct acpi_vector_group msi_group[MAX_IO_PICS];
>
> #define CORES_PER_EIO_NODE 4
>
> @@ -112,9 +114,8 @@ struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
> struct acpi_madt_ht_pic *acpi_htvec);
> int pch_lpc_acpi_init(struct irq_domain *parent,
> struct acpi_madt_lpc_pic *acpi_pchlpc);
> -struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
> - struct acpi_madt_msi_pic *acpi_pchmsi);
> int find_pch_pic(u32 gsi);
> +struct fwnode_handle *get_pch_msi_handle(int pci_segment);
>
> extern struct acpi_madt_lio_pic *acpi_liointc;
> extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
> @@ -127,7 +128,7 @@ struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
> extern struct irq_domain *cpu_domain;
> extern struct irq_domain *liointc_domain;
> extern struct fwnode_handle *pch_lpc_handle;
> -extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
> +extern struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
> extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
>
> extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
> index f2115be..82bc6c7 100644
> --- a/arch/loongarch/kernel/irq.c
> +++ b/arch/loongarch/kernel/irq.c
> @@ -27,8 +27,8 @@
>
> struct irq_domain *cpu_domain;
> struct irq_domain *liointc_domain;
> -struct irq_domain *pch_msi_domain[MAX_IO_PICS];
> struct acpi_vector_group pch_group[MAX_IO_PICS];
> +struct acpi_vector_group msi_group[MAX_IO_PICS];
>
> /*
> * 'what should we do if we get a hw irq event on an illegal vector'.
> @@ -55,6 +55,33 @@ int arch_show_interrupts(struct seq_file *p, int prec)
> return 0;
> }
>
> +static int early_pci_mcfg_parse(struct acpi_table_header *header)
Shouldn't this be __init as well?
> +{
> + struct acpi_table_mcfg *mcfg;
> + struct acpi_mcfg_allocation *mptr;
> + int i, n;
> +
> + if (header->length < sizeof(struct acpi_table_mcfg))
> + return -EINVAL;
> +
> + n = (header->length - sizeof(struct acpi_table_mcfg)) /
> + sizeof(struct acpi_mcfg_allocation);
> + mcfg = (struct acpi_table_mcfg *)header;
> + mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
> +
> + for (i = 0; i < n; i++, mptr++) {
> + msi_group[i].pci_segment = mptr->pci_segment;
> + msi_group[i].node = (mptr->address >> 44) & 0xf;
> + }
> +
> + return 0;
> +}
> +
> +void __init init_msi_parent_group(void)
> +{
> + acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
> +}
> +
> void __init init_IRQ(void)
> {
> int i;
> @@ -68,6 +95,7 @@ void __init init_IRQ(void)
> clear_csr_ecfg(ECFG0_IM);
> clear_csr_estat(ESTATF_IP);
>
> + init_msi_parent_group();
The changes in this file should be a separate patch, as it is
completely independent.
> irqchip_init();
> #ifdef CONFIG_SMP
> ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
> diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-loongson-pch-msi.c
> index e3801c4..5db4a68 100644
> --- a/drivers/irqchip/irq-loongson-pch-msi.c
> +++ b/drivers/irqchip/irq-loongson-pch-msi.c
> @@ -15,14 +15,30 @@
> #include <linux/pci.h>
> #include <linux/slab.h>
>
> +static int nr_pics;
> +
> struct pch_msi_data {
> struct mutex msi_map_lock;
> phys_addr_t doorbell;
> u32 irq_first; /* The vector number that MSIs starts */
> u32 num_irqs; /* The number of vectors for MSIs */
> unsigned long *msi_map;
> + struct fwnode_handle *domain_handle;
> };
>
> +static struct pch_msi_data *pch_msi_priv[2];
What is this '2'?
> +
> +struct fwnode_handle *get_pch_msi_handle(int pci_segment)
> +{
> + int i;
> +
> + for (i = 0; i < MAX_IO_PICS; i++) {
> + if (msi_group[i].pci_segment == pci_segment)
AFAICT, this driver is supposed to compile on MIPS too. Clearly, you
haven't bothered checking that it was still building:
drivers/irqchip/irq-loongson-pch-msi.c: In function ‘get_pch_msi_handle’:
drivers/irqchip/irq-loongson-pch-msi.c:35:18: error: ‘MAX_IO_PICS’ undeclared (first use in this function)
35 | for (i = 0; i < MAX_IO_PICS; i++) {
| ^~~~~~~~~~~
drivers/irqchip/irq-loongson-pch-msi.c:35:18: note: each undeclared identifier is reported only once for each function it appears in
drivers/irqchip/irq-loongson-pch-msi.c:36:7: error: ‘msi_group’ undeclared (first use in this function); did you mean ‘task_group’?
36 | if (msi_group[i].pci_segment == pci_segment)
| ^~~~~~~~~
| task_group
I've stopped here.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 07/13] irqchip/loongson-pch-msi: Add ACPI init support
2022-06-29 13:15 ` Marc Zyngier
@ 2022-06-30 2:51 ` Jianmin Lv
0 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-30 2:51 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On 2022/6/29 下午9:15, Marc Zyngier wrote:
> On Mon, 27 Jun 2022 12:39:51 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> We are preparing to add new Loongson (based on LoongArch, not compatible
>> with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
>> as its boot protocol, so add ACPI init support.
>
> Same rant about the content-less paragraph, which I asked you to drop
> a few version ago.
>
Ok, I only dropped it for the patch that you reviewed in previous
version, without handling other similar patches. I'll drop it for all
similar patch in next version.
>>
>> PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
>> Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
>> please refer Documentation/loongarch/irq-chip-model.rst.
>>
>> For systems with two chipsets, there are two related msi irqdomains,
>> each of which has the same node id as its parent irqdomain. So we
>> use a structure to mantain the relation of node and it's parent
>> irqdomain as pch irqdomin, and add a pci_segment field to it for
>> matching the pci segment of a pci device when setting msi irqdomain
>> for the device.
>>
>> struct acpi_vector_group {
>> int node;
>> int pci_segment;
>> struct irq_domain *parent;
>> };
>>
>> The field 'pci_segment' and 'node' are initialized from MCFG, and
>> the parent irqdomain will set field 'parent' by matching same
>> 'node'.
>>
>> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>> ---
>> arch/loongarch/include/asm/irq.h | 7 +-
>> arch/loongarch/kernel/irq.c | 30 ++++++-
>> drivers/irqchip/irq-loongson-pch-msi.c | 147 +++++++++++++++++++++++----------
>> 3 files changed, 138 insertions(+), 46 deletions(-)
>>
>> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
>> index a444dc6..367aa44 100644
>> --- a/arch/loongarch/include/asm/irq.h
>> +++ b/arch/loongarch/include/asm/irq.h
>> @@ -50,9 +50,11 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
>>
>> struct acpi_vector_group {
>> int node;
>> + int pci_segment;
>> struct irq_domain *parent;
>> };
>> extern struct acpi_vector_group pch_group[MAX_IO_PICS];
>> +extern struct acpi_vector_group msi_group[MAX_IO_PICS];
>>
>> #define CORES_PER_EIO_NODE 4
>>
>> @@ -112,9 +114,8 @@ struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_ht_pic *acpi_htvec);
>> int pch_lpc_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_lpc_pic *acpi_pchlpc);
>> -struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
>> - struct acpi_madt_msi_pic *acpi_pchmsi);
>> int find_pch_pic(u32 gsi);
>> +struct fwnode_handle *get_pch_msi_handle(int pci_segment);
>>
>> extern struct acpi_madt_lio_pic *acpi_liointc;
>> extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
>> @@ -127,7 +128,7 @@ struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
>> extern struct irq_domain *cpu_domain;
>> extern struct irq_domain *liointc_domain;
>> extern struct fwnode_handle *pch_lpc_handle;
>> -extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
>> +extern struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
>> extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
>>
>> extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
>> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
>> index f2115be..82bc6c7 100644
>> --- a/arch/loongarch/kernel/irq.c
>> +++ b/arch/loongarch/kernel/irq.c
>> @@ -27,8 +27,8 @@
>>
>> struct irq_domain *cpu_domain;
>> struct irq_domain *liointc_domain;
>> -struct irq_domain *pch_msi_domain[MAX_IO_PICS];
>> struct acpi_vector_group pch_group[MAX_IO_PICS];
>> +struct acpi_vector_group msi_group[MAX_IO_PICS];
>>
>> /*
>> * 'what should we do if we get a hw irq event on an illegal vector'.
>> @@ -55,6 +55,33 @@ int arch_show_interrupts(struct seq_file *p, int prec)
>> return 0;
>> }
>>
>> +static int early_pci_mcfg_parse(struct acpi_table_header *header)
>
> Shouldn't this be __init as well?
>
Yes, thanks, it should be __init too.
>> +{
>> + struct acpi_table_mcfg *mcfg;
>> + struct acpi_mcfg_allocation *mptr;
>> + int i, n;
>> +
>> + if (header->length < sizeof(struct acpi_table_mcfg))
>> + return -EINVAL;
>> +
>> + n = (header->length - sizeof(struct acpi_table_mcfg)) /
>> + sizeof(struct acpi_mcfg_allocation);
>> + mcfg = (struct acpi_table_mcfg *)header;
>> + mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
>> +
>> + for (i = 0; i < n; i++, mptr++) {
>> + msi_group[i].pci_segment = mptr->pci_segment;
>> + msi_group[i].node = (mptr->address >> 44) & 0xf;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +void __init init_msi_parent_group(void)
>> +{
>> + acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
>> +}
>> +
>> void __init init_IRQ(void)
>> {
>> int i;
>> @@ -68,6 +95,7 @@ void __init init_IRQ(void)
>> clear_csr_ecfg(ECFG0_IM);
>> clear_csr_estat(ESTATF_IP);
>>
>> + init_msi_parent_group();
>
> The changes in this file should be a separate patch, as it is
> completely independent.
>
Ok, I'll put it in a separate patch.
>> irqchip_init();
>> #ifdef CONFIG_SMP
>> ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
>> diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-loongson-pch-msi.c
>> index e3801c4..5db4a68 100644
>> --- a/drivers/irqchip/irq-loongson-pch-msi.c
>> +++ b/drivers/irqchip/irq-loongson-pch-msi.c
>> @@ -15,14 +15,30 @@
>> #include <linux/pci.h>
>> #include <linux/slab.h>
>>
>> +static int nr_pics;
>> +
>> struct pch_msi_data {
>> struct mutex msi_map_lock;
>> phys_addr_t doorbell;
>> u32 irq_first; /* The vector number that MSIs starts */
>> u32 num_irqs; /* The number of vectors for MSIs */
>> unsigned long *msi_map;
>> + struct fwnode_handle *domain_handle;
>> };
>>
>> +static struct pch_msi_data *pch_msi_priv[2];
>
> What is this '2'?
>
Yes, I should use MAX_IO_PICS, thanks.
>> +
>> +struct fwnode_handle *get_pch_msi_handle(int pci_segment)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < MAX_IO_PICS; i++) {
>> + if (msi_group[i].pci_segment == pci_segment)
>
> AFAICT, this driver is supposed to compile on MIPS too. Clearly, you
> haven't bothered checking that it was still building:
>
> drivers/irqchip/irq-loongson-pch-msi.c: In function ‘get_pch_msi_handle’:
> drivers/irqchip/irq-loongson-pch-msi.c:35:18: error: ‘MAX_IO_PICS’ undeclared (first use in this function)
> 35 | for (i = 0; i < MAX_IO_PICS; i++) {
> | ^~~~~~~~~~~
> drivers/irqchip/irq-loongson-pch-msi.c:35:18: note: each undeclared identifier is reported only once for each function it appears in
> drivers/irqchip/irq-loongson-pch-msi.c:36:7: error: ‘msi_group’ undeclared (first use in this function); did you mean ‘task_group’?
> 36 | if (msi_group[i].pci_segment == pci_segment)
> | ^~~~~~~~~
> | task_group
>
> I've stopped here.
So sorry for that, I got it, I'll fix them and test on both of LoongArch
and MIPS machine.
>
> M.
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 09/13] irqchip/loongson-liointc: Add ACPI init support
2022-06-29 13:13 ` Marc Zyngier
@ 2022-06-30 2:52 ` Jianmin Lv
0 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-30 2:52 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On 2022/6/29 下午9:13, Marc Zyngier wrote:
> On Mon, 27 Jun 2022 12:39:53 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> We are preparing to add new Loongson (based on LoongArch, not compatible
>> with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
>> as its boot protocol, so add ACPI init support.
>>
>> LIOINTC stands for "Legacy I/O Interrupts" that described in Section
>> 11.1 of "Loongson 3A5000 Processor Reference Manual". For more
>> information please refer Documentation/loongarch/irq-chip-model.rst.
>
> This is what happens with this series while compiling for MIPS:
>
> drivers/irqchip/irq-loongson-liointc.c: In function ‘liointc_domain_xlate’:
> drivers/irqchip/irq-loongson-liointc.c:170:28: error: ‘GSI_MIN_CPU_IRQ’ undeclared (first use in this function)
> 170 | *out_hwirq = intspec[0] - GSI_MIN_CPU_IRQ;
> | ^~~~~~~~~~~~~~~
>
> I haven't bothered reviewing more patches, as this is a waste of my
> time.
>
Sorry for wasting your time, Marc, I just test on my LoongArch machine,
I'll fix them and test on both of LoongArch and MIPS machine in future.
> M.
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 06/13] irqchip/loongson-pch-pic: Add ACPI init support
2022-06-29 11:20 ` Marc Zyngier
@ 2022-06-30 4:36 ` Jianmin Lv
2022-06-30 7:22 ` Marc Zyngier
0 siblings, 1 reply; 26+ messages in thread
From: Jianmin Lv @ 2022-06-30 4:36 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On 2022/6/29 下午7:20, Marc Zyngier wrote:
> On Mon, 27 Jun 2022 12:39:50 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> We are preparing to add new Loongson (based on LoongArch, not compatible
>> with old MIPS-based Loongson) support. LoongArch use ACPI other than DT
>> as its boot protocol, so add ACPI init support.
>
> Drop this paragraph.
>
Ok, I'll drop it for the patch and other patches of this series.
>>
>> PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
>> Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
>> please refer Documentation/loongarch/irq-chip-model.rst.
>>
>> For systems with two chipsets, there are two related pch irqdomains,
>> each of which has the same node id as its parent irqdomain. So we
>> defined a structure to mantain the relation of node and it's parent
>> irqdomain.
>>
>> struct acpi_vector_group {
>> int node;
>> struct irq_domain *parent;
>> };
>>
>> The parent irqdomain will be set for node id in parent irqdomain driver
>> before pch irqdomain is created.
>>
>> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>> ---
>> arch/loongarch/include/asm/irq.h | 11 +-
>> arch/loongarch/kernel/irq.c | 2 +-
>> drivers/irqchip/irq-loongson-pch-pic.c | 200 ++++++++++++++++++++++++++++-----
>> 3 files changed, 179 insertions(+), 34 deletions(-)
>>
>> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
>> index 48c0ce4..a444dc6 100644
>> --- a/arch/loongarch/include/asm/irq.h
>> +++ b/arch/loongarch/include/asm/irq.h
>> @@ -48,6 +48,12 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
>> #define MAX_IO_PICS 2
>> #define NR_IRQS (64 + (256 * MAX_IO_PICS))
>>
>> +struct acpi_vector_group {
>> + int node;
>> + struct irq_domain *parent;
>> +};
>> +extern struct acpi_vector_group pch_group[MAX_IO_PICS];
>> +
>> #define CORES_PER_EIO_NODE 4
>>
>> #define LOONGSON_CPU_UART0_VEC 10 /* CPU UART0 */
>> @@ -108,8 +114,7 @@ int pch_lpc_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_lpc_pic *acpi_pchlpc);
>> struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_msi_pic *acpi_pchmsi);
>> -struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
>> - struct acpi_madt_bio_pic *acpi_pchpic);
>> +int find_pch_pic(u32 gsi);
>>
>> extern struct acpi_madt_lio_pic *acpi_liointc;
>> extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
>> @@ -123,7 +128,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
>> extern struct irq_domain *liointc_domain;
>> extern struct fwnode_handle *pch_lpc_handle;
>> extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
>> -extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
>> +extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
>>
>> extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
>>
>> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
>> index 07d6059..f2115be 100644
>> --- a/arch/loongarch/kernel/irq.c
>> +++ b/arch/loongarch/kernel/irq.c
>> @@ -28,7 +28,7 @@
>> struct irq_domain *cpu_domain;
>> struct irq_domain *liointc_domain;
>> struct irq_domain *pch_msi_domain[MAX_IO_PICS];
>> -struct irq_domain *pch_pic_domain[MAX_IO_PICS];
>> +struct acpi_vector_group pch_group[MAX_IO_PICS];
>>
>> /*
>> * 'what should we do if we get a hw irq event on an illegal vector'.
>> diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
>> index a4eb8a2..170a5b9 100644
>> --- a/drivers/irqchip/irq-loongson-pch-pic.c
>> +++ b/drivers/irqchip/irq-loongson-pch-pic.c
>> @@ -33,13 +33,40 @@
>> #define PIC_REG_IDX(irq_id) ((irq_id) / PIC_COUNT_PER_REG)
>> #define PIC_REG_BIT(irq_id) ((irq_id) % PIC_COUNT_PER_REG)
>>
>> +static int nr_pics;
>> +
>> struct pch_pic {
>> void __iomem *base;
>> struct irq_domain *pic_domain;
>> + struct fwnode_handle *domain_handle;
>> u32 ht_vec_base;
>> raw_spinlock_t pic_lock;
>> + u32 gsi_end;
>> + u32 gsi_base;
>> };
>>
>> +static struct pch_pic *pch_pic_priv[2];
>
> Why 2? Is that related to MAX_IO_PICS being 2?
>
Yes, thanks, I should use MAX_IO_PICS for it.
>> +struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
>> +
>> +int find_pch_pic(u32 gsi)
>> +{
>> + int i;
>> +
>> + /* Find the PCH_PIC that manages this GSI. */
>> + for (i = 0; i < MAX_IO_PICS; i++) {
>> + struct pch_pic *priv = pch_pic_priv[i];
>> +
>> + if (!priv)
>> + return -1;
>> +
>> + if (gsi >= priv->gsi_base && gsi <= priv->gsi_end)
>> + return i;
>> + }
>> +
>> + pr_err("ERROR: Unable to locate PCH_PIC for GSI %d\n", gsi);
>> + return -1;
>> +}
>> +
>> static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)
>> {
>> u32 reg;
>> @@ -139,6 +166,24 @@ static void pch_pic_ack_irq(struct irq_data *d)
>> .irq_set_type = pch_pic_set_type,
>> };
>>
>> +static int pch_pic_domain_translate(struct irq_domain *d,
>> + struct irq_fwspec *fwspec,
>> + unsigned long *hwirq,
>> + unsigned int *type)
>> +{
>> + struct pch_pic *priv = d->host_data;
>> + struct device_node *of_node = to_of_node(fwspec->fwnode);
>> +
>> + if (fwspec->param_count < 1)
>> + return -EINVAL;
>> + if (of_node)
>> + *hwirq += priv->ht_vec_base;
>> + else
>> + *hwirq = fwspec->param[0] - priv->gsi_base;
>> + *type = IRQ_TYPE_NONE;
>
> Have you tested this on MIPS HW? This looks like a regression on the
> OF path, as it used irq_domain_translate_twocell().
>
No, I don't test on MIPS for this version patch, I want to use 'of_node'
to distinguish MIPS and LoongArch, but it seems that there is still
other problem, I'll fix it as following in next version and test it on MIPS.
if (of_node) {
*hwirq = fwspec->param[0] + priv->ht_vec_base;
*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
} else {
*hwirq = fwspec->param[0] - priv->gsi_base;
*type = IRQ_TYPE_NONE;
}
>> +
>> + return 0;
>> +}
>> static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
>> unsigned int nr_irqs, void *arg)
>> {
>> @@ -149,13 +194,13 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
>> struct irq_fwspec parent_fwspec;
>> struct pch_pic *priv = domain->host_data;
>>
>> - err = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
>> + err = pch_pic_domain_translate(domain, fwspec, &hwirq, &type);
>> if (err)
>> return err;
>>
>> parent_fwspec.fwnode = domain->parent->fwnode;
>> parent_fwspec.param_count = 1;
>> - parent_fwspec.param[0] = hwirq + priv->ht_vec_base;
>> + parent_fwspec.param[0] = hwirq;
>>
>> err = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
>> if (err)
>> @@ -170,7 +215,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
>> }
>>
>> static const struct irq_domain_ops pch_pic_domain_ops = {
>> - .translate = irq_domain_translate_twocell,
>> + .translate = pch_pic_domain_translate,
>> .alloc = pch_pic_alloc,
>> .free = irq_domain_free_irqs_parent,
>> };
>> @@ -180,7 +225,7 @@ static void pch_pic_reset(struct pch_pic *priv)
>> int i;
>>
>> for (i = 0; i < PIC_COUNT; i++) {
>> - /* Write vectored ID */
>> + /* Write vector ID */
>> writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i));
>> /* Hardcode route to HT0 Lo */
>> writeb(1, priv->base + PCH_INT_ROUTE(i));
>> @@ -198,50 +243,41 @@ static void pch_pic_reset(struct pch_pic *priv)
>> }
>> }
>>
>> -static int pch_pic_of_init(struct device_node *node,
>> - struct device_node *parent)
>> +static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base,
>> + struct irq_domain *parent_domain, struct fwnode_handle *domain_handle,
>> + u32 gsi_base)
>> {
>> + int vec_count;
>> struct pch_pic *priv;
>> - struct irq_domain *parent_domain;
>> - int err;
>>
>> priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>> if (!priv)
>> return -ENOMEM;
>>
>> raw_spin_lock_init(&priv->pic_lock);
>> - priv->base = of_iomap(node, 0);
>> - if (!priv->base) {
>> - err = -ENOMEM;
>> + priv->base = ioremap(addr, size);
>> + if (!priv->base)
>> goto free_priv;
>> - }
>>
>> - parent_domain = irq_find_host(parent);
>> - if (!parent_domain) {
>> - pr_err("Failed to find the parent domain\n");
>> - err = -ENXIO;
>> - goto iounmap_base;
>> - }
>> + priv->domain_handle = domain_handle;
>>
>> - if (of_property_read_u32(node, "loongson,pic-base-vec",
>> - &priv->ht_vec_base)) {
>> - pr_err("Failed to determine pic-base-vec\n");
>> - err = -EINVAL;
>> - goto iounmap_base;
>> - }
>> + priv->ht_vec_base = vec_base;
>
> Why isn't this pre-filled on the OF path as it isn't relevant to ACPI?
>
No, ht_vec_base is required for both of OF and ACPI.
pch_pic_init is called from pch_pic_of_init for OF path and from
pch_pic_init_irqdomain for ACPI path, so the 'vec_base' is passed into
pch_pic_init to pre-fill 'ht_vec_base' from both path.
>> + vec_count = ((readq(priv->base) >> 48) & 0xff) + 1;
>
> Is that valid on the old HW?
>
Yes.
>> + priv->gsi_base = gsi_base;
>
> Why isn't this pre-filled on the ACPI path as it isn't relevant to OF?
>
Yes, it's only for ACPI.
>> + priv->gsi_end = gsi_base + vec_count - 1;
>
> I don't think this needs to be ACPI specific. Just track the vector
> count, which applies to both ACPI and DT.
>
Agree, thanks for your suggestion, tracking vector count is enough for both.
>>
>> priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0,
>> - PIC_COUNT,
>> - of_node_to_fwnode(node),
>> - &pch_pic_domain_ops,
>> - priv);
>> + vec_count, priv->domain_handle,
>> + &pch_pic_domain_ops, priv);
>> +
>> if (!priv->pic_domain) {
>> pr_err("Failed to create IRQ domain\n");
>> - err = -ENOMEM;
>> goto iounmap_base;
>> }
>>
>> pch_pic_reset(priv);
>> + pch_pic_handle[nr_pics] = domain_handle;
>> + pch_pic_priv[nr_pics++] = priv;
>>
>> return 0;
>>
>> @@ -250,7 +286,111 @@ static int pch_pic_of_init(struct device_node *node,
>> free_priv:
>> kfree(priv);
>>
>> - return err;
>> + return -EINVAL;
>> +}
>> +
>> +#ifdef CONFIG_OF
>> +
>> +static int pch_pic_of_init(struct device_node *node,
>> + struct device_node *parent)
>> +{
>> + int err, vec_base;
>> + struct resource res;
>> + struct irq_domain *parent_domain;
>> +
>> + if (of_address_to_resource(node, 0, &res))
>> + return -EINVAL;
>> +
>> + parent_domain = irq_find_host(parent);
>> + if (!parent_domain) {
>> + pr_err("Failed to find the parent domain\n");
>> + return -ENXIO;
>> + }
>> +
>> + if (of_property_read_u32(node, "loongson,pic-base-vec", &vec_base)) {
>> + pr_err("Failed to determine pic-base-vec\n");
>> + return -EINVAL;
>> + }
>> +
>> + err = pch_pic_init(res.start, resource_size(&res), vec_base,
>> + parent_domain, of_node_to_fwnode(node), 0);
>> + if (err < 0)
>> + return err;
>> +
>> + return 0;
>> }
>>
>> IRQCHIP_DECLARE(pch_pic, "loongson,pch-pic-1.0", pch_pic_of_init);
>> +
>> +#endif
>> +
>> +#ifdef CONFIG_ACPI
>> +static int __init
>> +lpcintc_parse_madt(union acpi_subtable_headers *header,
>> + const unsigned long end)
>> +{
>> + struct acpi_madt_lpc_pic *lpcintc_entry = (struct acpi_madt_lpc_pic *)header;
>> +
>> + return pch_lpc_acpi_init(pch_pic_priv[0]->pic_domain, lpcintc_entry);
>> +}
>> +
>> +static int __init acpi_cascade_irqdomain_init(void)
>> +{
>> + acpi_table_parse_madt(ACPI_MADT_TYPE_LPC_PIC,
>> + lpcintc_parse_madt, 0);
>> + return 0;
>> +}
>
> Missing blank line between functions
>
Ok, thanks for your correction.
>> +int __init pch_pic_init_irqdomain(struct irq_domain *parent,
>> + struct acpi_madt_bio_pic *acpi_pchpic)
>> +{
>> + int ret, vec_base;
>> + struct fwnode_handle *domain_handle;
>> +
>> + if (!acpi_pchpic)
>> + return -EINVAL;
>> +
>> + vec_base = acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ;
>> +
>> + domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchpic);
>> + if (!domain_handle) {
>> + pr_err("Unable to allocate domain handle\n");
>> + return -ENOMEM;
>> + }
>> +
>> + ret = pch_pic_init(acpi_pchpic->address, acpi_pchpic->size,
>> + vec_base, parent, domain_handle, acpi_pchpic->gsi_base);
>> + if (ret == 0 && acpi_pchpic->id == 0)
>> + acpi_cascade_irqdomain_init();
>> +
>> + return ret;
>> +}
>> +
>> +struct irq_domain *acpi_get_pch_parent(int node)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < MAX_IO_PICS; i++) {
>> + if (node == pch_group[i].node)
>> + return pch_group[i].parent;
>> + }
>> + return NULL;
>> +}
>> +
>> +static int __init pchintc_parse_madt(union acpi_subtable_headers *header,
>> + const unsigned long end)
>> +{
>> + struct acpi_madt_bio_pic *pch_pic_entry = (struct acpi_madt_bio_pic *)header;
>> +
>> + return pch_pic_init_irqdomain(acpi_get_pch_parent((pch_pic_entry->address >> 44) & 0xf),
>> + pch_pic_entry);
>> +}
>> +
>> +static int __init pch_pic_acpi_init(void)
>> +{
>> + acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
>
> Where is this defined? It only appears in the documentation, and
> nowhere else...
>
It's defined in the patch to ACPICA(which has been merged, please to see
https://github.com/acpica/acpica/commit/1dc530059a3e6202e941e6a9478cf30f092bfb47).
the patch will be synchronized to linux kernel by maintainer of ACPICA.
>> + pchintc_parse_madt, 0);
>> +
>> + return 0;
>> +}
>> +early_initcall(pch_pic_acpi_init);
>
> Why can't you use IRQCHIP_ACPI_DECLARE here? This is terribly fragile,
> and will eventually break. I really don't want to rely on this.
>
In early time, the change here is implemented using
IRQCHIP_ACPI_DECLARE, but we found that calling order(during
irqchip_init) of the entry declared using IRQCHIP_ACPI_DECLARE is
depended on the compiling order(driver order in Makefile) of the driver.
For removing the dependency to the compiling order, the new way here is
used(I looked into ARM, it seems that GIC driver uses
IRQCHIP_ACPI_DECLARE, and ITS driver uses early_initcall too.).
> M.
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 05/13] irqchip: Add Loongson PCH LPC controller support
2022-06-29 10:58 ` Marc Zyngier
@ 2022-06-30 4:40 ` Jianmin Lv
0 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-30 4:40 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On 2022/6/29 下午6:58, Marc Zyngier wrote:
> On Mon, 27 Jun 2022 12:39:49 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> PCH-LPC stands for "LPC Interrupts" that described in Section 24.3 of
>> "Loongson 7A1000 Bridge User Manual". For more information please refer
>> Documentation/loongarch/irq-chip-model.rst.
>>
>> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>> ---
>> arch/loongarch/include/asm/irq.h | 4 +-
>> arch/loongarch/kernel/irq.c | 1 -
>> drivers/irqchip/Kconfig | 8 ++
>> drivers/irqchip/Makefile | 1 +
>> drivers/irqchip/irq-loongson-pch-lpc.c | 203 +++++++++++++++++++++++++++++++++
>> 5 files changed, 214 insertions(+), 3 deletions(-)
>> create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c
>>
>> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
>> index ace3ea6..48c0ce4 100644
>> --- a/arch/loongarch/include/asm/irq.h
>> +++ b/arch/loongarch/include/asm/irq.h
>> @@ -104,7 +104,7 @@ struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
>>
>> struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_ht_pic *acpi_htvec);
>> -struct irq_domain *pch_lpc_acpi_init(struct irq_domain *parent,
>> +int pch_lpc_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_lpc_pic *acpi_pchlpc);
>> struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_msi_pic *acpi_pchmsi);
>> @@ -121,7 +121,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
>>
>> extern struct irq_domain *cpu_domain;
>> extern struct irq_domain *liointc_domain;
>> -extern struct irq_domain *pch_lpc_domain;
>> +extern struct fwnode_handle *pch_lpc_handle;
>> extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
>> extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
>>
>> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
>> index b34b8d7..07d6059 100644
>> --- a/arch/loongarch/kernel/irq.c
>> +++ b/arch/loongarch/kernel/irq.c
>> @@ -27,7 +27,6 @@
>>
>> struct irq_domain *cpu_domain;
>> struct irq_domain *liointc_domain;
>> -struct irq_domain *pch_lpc_domain;
>> struct irq_domain *pch_msi_domain[MAX_IO_PICS];
>> struct irq_domain *pch_pic_domain[MAX_IO_PICS];
>>
>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>> index 1f23a6b..c1d527f 100644
>> --- a/drivers/irqchip/Kconfig
>> +++ b/drivers/irqchip/Kconfig
>> @@ -591,6 +591,14 @@ config LOONGSON_PCH_MSI
>> help
>> Support for the Loongson PCH MSI Controller.
>>
>> +config LOONGSON_PCH_LPC
>> + bool "Loongson PCH LPC Controller"
>> + depends on MACH_LOONGSON64
>> + default (MACH_LOONGSON64 && LOONGARCH)
>> + select IRQ_DOMAIN_HIERARCHY
>> + help
>> + Support for the Loongson PCH LPC Controller.
>> +
>> config MST_IRQ
>> bool "MStar Interrupt Controller"
>> depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>> index 5b67450..242b8b3 100644
>> --- a/drivers/irqchip/Makefile
>> +++ b/drivers/irqchip/Makefile
>> @@ -108,6 +108,7 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
>> obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
>> obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
>> obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
>> +obj-$(CONFIG_LOONGSON_PCH_LPC) += irq-loongson-pch-lpc.o
>> obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
>> obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o
>> obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
>> diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
>> new file mode 100644
>> index 0000000..7e4d89a
>> --- /dev/null
>> +++ b/drivers/irqchip/irq-loongson-pch-lpc.c
>> @@ -0,0 +1,203 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Loongson LPC Interrupt Controller support
>> + *
>> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
>> + */
>> +
>> +#define pr_fmt(fmt) "lpc: " fmt
>> +
>> +#include <linux/interrupt.h>
>> +#include <linux/irq.h>
>> +#include <linux/irqchip.h>
>> +#include <linux/irqchip/chained_irq.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/kernel.h>
>> +
>> +/* Registers */
>> +#define LPC_INT_CTL 0x00
>> +#define LPC_INT_ENA 0x04
>> +#define LPC_INT_STS 0x08
>> +#define LPC_INT_CLR 0x0c
>> +#define LPC_INT_POL 0x10
>> +#define LPC_COUNT 16
>> +
>> +struct pch_lpc {
>> + void __iomem *base;
>> + struct irq_domain *lpc_domain;
>> + raw_spinlock_t lpc_lock;
>> + u32 saved_reg_ctl;
>> + u32 saved_reg_ena;
>> + u32 saved_reg_pol;
>> +};
>> +
>> +struct fwnode_handle *pch_lpc_handle;
>> +
>> +static void ack_lpc_irq(struct irq_data *d)
>> +{
>> + unsigned long flags;
>> + struct pch_lpc *priv = d->domain->host_data;
>> +
>> + raw_spin_lock_irqsave(&priv->lpc_lock, flags);
>> + writel(0x1 << d->hwirq, priv->base + LPC_INT_CLR);
>> + raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
>> +}
>> +static void mask_lpc_irq(struct irq_data *d)
>> +{
>> + unsigned long flags;
>> + struct pch_lpc *priv = d->domain->host_data;
>> +
>> + raw_spin_lock_irqsave(&priv->lpc_lock, flags);
>> + writel(readl(priv->base + LPC_INT_ENA) & (~(0x1 << (d->hwirq))),
>> + priv->base + LPC_INT_ENA);
>> + raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
>> +}
>> +
>> +static void unmask_lpc_irq(struct irq_data *d)
>> +{
>> + unsigned long flags;
>> + struct pch_lpc *priv = d->domain->host_data;
>> +
>> + raw_spin_lock_irqsave(&priv->lpc_lock, flags);
>> + writel(readl(priv->base + LPC_INT_ENA) | (0x1 << (d->hwirq)),
>> + priv->base + LPC_INT_ENA);
>> + raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
>> +}
>> +
>> +static int lpc_set_type(struct irq_data *d, unsigned int type)
>> +{
>> + u32 val;
>> + u32 mask = 0x1 << (d->hwirq);
>> + struct pch_lpc *priv = d->domain->host_data;
>> +
>> + if (!(type & IRQ_TYPE_LEVEL_MASK))
>> + return 0;
>> +
>> + val = readl(priv->base + LPC_INT_POL);
>> +
>> + if (type == IRQ_TYPE_LEVEL_HIGH)
>> + val |= mask;
>> + else
>> + val &= ~mask;
>> +
>> + writel(val, priv->base + LPC_INT_POL);
>> +
>> + return 0;
>> +}
>> +
>> +static struct irq_chip pch_lpc_irq_chip = {
>
> Make this const.
>
Ok, thanks.
>> + .name = "PCH LPC",
>> + .irq_mask = mask_lpc_irq,
>> + .irq_unmask = unmask_lpc_irq,
>> + .irq_ack = ack_lpc_irq,
>> + .irq_set_type = lpc_set_type,
>
> nit: please use the same format for all callbacks: lpc_irq_OPERATION
> (lpc_irq_mask, lpc_irq_set_type...), which makes it much easier to
> read.
>
Ok.
>> + .flags = IRQCHIP_SKIP_SET_WAKE,
>> +};
>> +
>> +static void lpc_irq_dispatch(struct irq_desc *desc)
>> +{
>> + u32 pending, bit, virq;
>> + struct irq_chip *chip = irq_desc_get_chip(desc);
>> + struct pch_lpc *priv = irq_desc_get_handler_data(desc);
>> +
>> + chained_irq_enter(chip, desc);
>> +
>> + pending = readl(priv->base + LPC_INT_ENA);
>> + pending &= readl(priv->base + LPC_INT_STS);
>> + if (!pending)
>> + spurious_interrupt();
>> +
>> + while (pending) {
>> + bit = __ffs(pending);
>> + virq = irq_linear_revmap(priv->lpc_domain, bit);
>> +
>> + generic_handle_irq(bit);
>
> Replace the whole thing with a call to generic_handle_domain_irq(). No
> new code should ever have to use generic_handle_irq().
>
Ok, thanks, got it.
>> + pending &= ~BIT(bit);
>> + }
>> + chained_irq_exit(chip, desc);
>> +}
>> +
>> +static int pch_lpc_map(struct irq_domain *d, unsigned int irq,
>> + irq_hw_number_t hw)
>> +{
>> + irq_set_chip_and_handler(irq, &pch_lpc_irq_chip, handle_level_irq);
>> + return 0;
>> +}
>> +
>> +static const struct irq_domain_ops pch_lpc_domain_ops = {
>> + .map = pch_lpc_map,
>> + .translate = irq_domain_translate_twocell,
>> +};
>> +
>> +static void pch_lpc_reset(struct pch_lpc *priv)
>> +{
>> + /* Enable the LPC interrupt, bit31: en bit30: edge */
>> + writel(0x80000000, priv->base + LPC_INT_CTL);
>
> Please don't hardcode numbers. Add the proper bit definitions.
>
Ok.
>> + writel(0, priv->base + LPC_INT_ENA);
>> + /* Clear all 18-bit interrpt bit */
>> + writel(0x3ffff, priv->base + LPC_INT_CLR);
>
> If that's just a mask, then use GENMASK(17, 0) instead.
>
Ok.
>> +}
>> +
>> +static int pch_lpc_disabled(struct pch_lpc *priv)
>> +{
>> + return (readl(priv->base + LPC_INT_ENA) == 0xffffffff) &&
>> + (readl(priv->base + LPC_INT_STS) == 0xffffffff);
>> +}
>> +
>> +int __init pch_lpc_acpi_init(struct irq_domain *parent,
>> + struct acpi_madt_lpc_pic *acpi_pchlpc)
>> +{
>> + int parent_irq;
>> + struct pch_lpc *priv;
>> + struct irq_fwspec fwspec;
>> + struct fwnode_handle *irq_handle;
>> +
>> + if (!acpi_pchlpc)
>> + return -EINVAL;
>> +
>> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + raw_spin_lock_init(&priv->lpc_lock);
>> +
>> + priv->base = ioremap(acpi_pchlpc->address, acpi_pchlpc->size);
>> + if (!priv->base)
>> + goto free_priv;
>> +
>> + if (pch_lpc_disabled(priv)) {
>> + pr_err("Failed to get LPC status\n");
>> + goto iounmap_base;
>> + }
>> +
>> + irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
>> + if (!irq_handle) {
>> + pr_err("Unable to allocate domain handle\n");
>> + goto iounmap_base;
>> + }
>> +
>> + priv->lpc_domain = irq_domain_create_linear(irq_handle, LPC_COUNT,
>> + &pch_lpc_domain_ops, priv);
>> + if (!priv->lpc_domain) {
>> + pr_err("Failed to create IRQ domain\n");
>> + goto iounmap_base;
>
> You also need to free the fwnode.
>
Yes, thanks.
>> + }
>> + pch_lpc_reset(priv);
>> +
>> + fwspec.fwnode = parent->fwnode;
>> + fwspec.param[0] = acpi_pchlpc->cascade;
>> + fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
>> + fwspec.param_count = 2;
>> + parent_irq = irq_create_fwspec_mapping(&fwspec);
>> + irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv);
>> +
>> + pch_lpc_handle = irq_handle;
>> + return 0;
>> +
>> +iounmap_base:
>> + iounmap(priv->base);
>> +free_priv:
>> + kfree(priv);
>> +
>> + return -ENOMEM;
>> +}
>> --
>> 1.8.3.1
>>
>>
>
> Thanks,
>
> M.
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 06/13] irqchip/loongson-pch-pic: Add ACPI init support
2022-06-30 4:36 ` Jianmin Lv
@ 2022-06-30 7:22 ` Marc Zyngier
2022-06-30 8:37 ` Jianmin Lv
0 siblings, 1 reply; 26+ messages in thread
From: Marc Zyngier @ 2022-06-30 7:22 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On Thu, 30 Jun 2022 05:36:40 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
[...]
> >> +static int __init pch_pic_acpi_init(void)
> >> +{
> >> + acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
> >
> > Where is this defined? It only appears in the documentation, and
> > nowhere else...
> >
>
> It's defined in the patch to ACPICA(which has been merged, please to
> see
> https://github.com/acpica/acpica/commit/1dc530059a3e6202e941e6a9478cf30f092bfb47).
> the patch will be synchronized to linux kernel by maintainer of ACPICA.
How can I take this patch upstream if it doesn't even compile? Please
make this patch part of your series. There are tons of patches that
need Acks from the ACPI maintainers, this is only one of them.
>
>
> >> + pchintc_parse_madt, 0);
> >> +
> >> + return 0;
> >> +}
> >> +early_initcall(pch_pic_acpi_init);
> >
> > Why can't you use IRQCHIP_ACPI_DECLARE here? This is terribly fragile,
> > and will eventually break. I really don't want to rely on this.
> >
>
> In early time, the change here is implemented using
> IRQCHIP_ACPI_DECLARE, but we found that calling order(during
> irqchip_init) of the entry declared using IRQCHIP_ACPI_DECLARE is
> depended on the compiling order(driver order in Makefile) of the
> driver. For removing the dependency to the compiling order, the new
> way here is used(I looked into ARM, it seems that GIC driver uses
> IRQCHIP_ACPI_DECLARE, and ITS driver uses early_initcall too.).
It's not quite the same. The ITS part that uses early_initcall isn't
an actual driver (it only registers a domain, and nothing else).
There is also no guarantee that the initcalls at the same priority
will execute in any order, and you already have at least two such
initcalls (pch_pic_acpi_init, pch_msi_acpi_init, and I haven't quite
understood how the rest is probed yet).
One possibility would be to drive the whole probing from the root
interrupt controller, which is similar to what GICv3 does for the
actual ITS driver. You already do this sort of stuff in the CPUINTC
driver, so adding to this shouldn't be too hard.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V13 06/13] irqchip/loongson-pch-pic: Add ACPI init support
2022-06-30 7:22 ` Marc Zyngier
@ 2022-06-30 8:37 ` Jianmin Lv
0 siblings, 0 replies; 26+ messages in thread
From: Jianmin Lv @ 2022-06-30 8:37 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, linux-kernel, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
On 2022/6/30 下午3:22, Marc Zyngier wrote:
> On Thu, 30 Jun 2022 05:36:40 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>>
>
> [...]
>
>>>> +static int __init pch_pic_acpi_init(void)
>>>> +{
>>>> + acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
>>>
>>> Where is this defined? It only appears in the documentation, and
>>> nowhere else...
>>>
>>
>> It's defined in the patch to ACPICA(which has been merged, please to
>> see
>> https://github.com/acpica/acpica/commit/1dc530059a3e6202e941e6a9478cf30f092bfb47).
>> the patch will be synchronized to linux kernel by maintainer of ACPICA.
>
> How can I take this patch upstream if it doesn't even compile? Please
> make this patch part of your series. There are tons of patches that
> need Acks from the ACPI maintainers, this is only one of them.
>
Ok, I'll put the patch into my series.
>>
>>
>>>> + pchintc_parse_madt, 0);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +early_initcall(pch_pic_acpi_init);
>>>
>>> Why can't you use IRQCHIP_ACPI_DECLARE here? This is terribly fragile,
>>> and will eventually break. I really don't want to rely on this.
>>>
>>
>> In early time, the change here is implemented using
>> IRQCHIP_ACPI_DECLARE, but we found that calling order(during
>> irqchip_init) of the entry declared using IRQCHIP_ACPI_DECLARE is
>> depended on the compiling order(driver order in Makefile) of the
>> driver. For removing the dependency to the compiling order, the new
>> way here is used(I looked into ARM, it seems that GIC driver uses
>> IRQCHIP_ACPI_DECLARE, and ITS driver uses early_initcall too.).
>
> It's not quite the same. The ITS part that uses early_initcall isn't
> an actual driver (it only registers a domain, and nothing else).
>
Ok, thanks, I got it, I don't understand ARM's irqchips well.
> There is also no guarantee that the initcalls at the same priority
> will execute in any order, and you already have at least two such
> initcalls (pch_pic_acpi_init, pch_msi_acpi_init, and I haven't quite
> understood how the rest is probed yet).
>
Yes, agree, but pch_pic and pch_msi are independent, and there is no
dependencies between them, so there is no requirement on calling order
for the two entries.
> One possibility would be to drive the whole probing from the root
> interrupt controller, which is similar to what GICv3 does for the
> actual ITS driver. You already do this sort of stuff in the CPUINTC
> driver, so adding to this shouldn't be too hard.
>
Ok, thanks for your suggestion, I'll try to change it as the way in the
CPUINTC driver, it seems that way is better.
> M.
>
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2022-06-30 8:38 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-27 11:39 [PATCH V13 00/13] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 01/13] APCI: irq: Add support for multiple GSI domains Jianmin Lv
2022-06-28 12:50 ` Hanjun Guo
2022-06-27 11:39 ` [PATCH V13 02/13] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
2022-06-28 13:26 ` Hanjun Guo
2022-06-27 11:39 ` [PATCH V13 03/13] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 04/13] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 05/13] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
2022-06-29 10:58 ` Marc Zyngier
2022-06-30 4:40 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 06/13] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
2022-06-29 11:20 ` Marc Zyngier
2022-06-30 4:36 ` Jianmin Lv
2022-06-30 7:22 ` Marc Zyngier
2022-06-30 8:37 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 07/13] irqchip/loongson-pch-msi: " Jianmin Lv
2022-06-29 13:15 ` Marc Zyngier
2022-06-30 2:51 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 08/13] irqchip/loongson-htvec: " Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 09/13] irqchip/loongson-liointc: " Jianmin Lv
2022-06-29 13:13 ` Marc Zyngier
2022-06-30 2:52 ` Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 10/13] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 11/13] irqchip: Add LoongArch CPU " Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 12/13] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
2022-06-27 11:39 ` [PATCH V13 13/13] LoongArch: Fix irq number for timer and ipi Jianmin Lv
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