From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B52EC433F5 for ; Wed, 15 Sep 2021 15:10:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B46A261029 for ; Wed, 15 Sep 2021 15:10:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B46A261029 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:40844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQWYZ-0007q4-Ub for qemu-devel@archiver.kernel.org; Wed, 15 Sep 2021 11:10:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQWVK-0003ih-DT; Wed, 15 Sep 2021 11:07:18 -0400 Received: from mail.kernel.org ([198.145.29.99]:40834) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQWVG-000862-K1; Wed, 15 Sep 2021 11:07:17 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E8E0561029; Wed, 15 Sep 2021 15:07:11 +0000 (UTC) Received: from [198.52.44.129] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mQWVB-00AxRm-Sx; Wed, 15 Sep 2021 16:07:10 +0100 Date: Wed, 15 Sep 2021 16:07:07 +0100 Message-ID: <87v931c1yc.wl-maz@kernel.org> From: Marc Zyngier To: Alexander Graf Subject: Re: [PATCH v9 07/11] hvf: arm: Implement PSCI handling In-Reply-To: <4ce23412-7484-f77a-6378-4369b0b2397c@csgraf.de> References: <20210912230757.41096-1-agraf@csgraf.de> <20210912230757.41096-8-agraf@csgraf.de> <3132e2f5-41a6-6011-808b-7ea12abec1c0@csgraf.de> <87wnnib291.wl-maz@kernel.org> <4ce23412-7484-f77a-6378-4369b0b2397c@csgraf.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 198.52.44.129 X-SA-Exim-Rcpt-To: agraf@csgraf.de, peter.maydell@linaro.org, ehabkost@redhat.com, slp@redhat.com, philmd@redhat.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, dirty@apple.com, r.bolshakov@yadro.com, qemu-arm@nongnu.org, lfy@google.com, pbonzini@redhat.com, pcc@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Received-SPF: pass client-ip=198.145.29.99; envelope-from=maz@kernel.org; helo=mail.kernel.org X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Sergio Lopez , Peter Collingbourne , Richard Henderson , QEMU Developers , Cameron Esfahani , Roman Bolshakov , qemu-arm , Frank Yang , Paolo Bonzini , Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 15 Sep 2021 11:58:29 +0100, Alexander Graf wrote: > > > On 15.09.21 11:46, Marc Zyngier wrote: > > On Mon, 13 Sep 2021 13:30:57 +0100, > > Peter Maydell wrote: > >> On Mon, 13 Sept 2021 at 13:02, Alexander Graf wrote: > >>> > >>> On 13.09.21 13:44, Peter Maydell wrote: > >>>> On Mon, 13 Sept 2021 at 12:07, Alexander Graf wrote: > >>>>> To keep your train of thought though, what would you do if we encounter > >>>>> a conduit that is different from the chosen one? Today, I am aware of 2 > >>>>> different implementations: TCG injects #UD [1] while KVM sets x0 to -1 [2]. > >>>> If the SMC or HVC insn isn't being used for PSCI then it should > >>>> have its standard architectural behaviour. > >>> Why? > >> QEMU's assumption here is that there are basically two scenarios > >> for these instructions: > >> (1) we're providing an emulation of firmware that uses this > >> instruction (and only this insn, not the other one) to > >> provide PSCI services > >> (2) we're not emulating any firmware at all, we're running it > >> in the guest, and that guest firmware is providing PSCI > >> > >> In case (1) we provide a PSCI ABI on the end of the insn. > >> In case (2) we provide the architectural behaviour for the insn > >> so that the guest firmware can use it. > >> > >> We don't currently have > >> (3) we're providing an emulation of firmware that does something > >> other than providing PSCI services on this instruction > >> > >> which is what I think you're asking for. (Alternatively, you might > >> be after "provide PSCI via SMC, not HVC", ie use a different conduit. > >> If hvf documents that SMC is guaranteed to trap that would be > >> possible, I guess.) > >> > >>> Also, why does KVM behave differently? > >> Looks like Marc made KVM set x0 to -1 for SMC calls in kernel commit > >> c0938c72f8070aa; conveniently he's on the cc list here so we can > >> ask him :-) > > If we got a SMC trap into KVM, that's because the HW knows about it, > > so injecting an UNDEF is rather counter productive (we don't hide the > > fact that EL3 actually exists). > > > This is the part where you and Peter disagree :). What would you suggest > to do to create consistency between KVM and TCG based EL0/1 only VMs? I don't think we disagree. We simply have different implementation choices. The KVM "firmware" can only be used with HVC, and not SMC. SMC is reserved for cases where the guest talks to the actual EL3, or an emulation of it in the case of NV. As for consistency between TGC and KVM, I have no plan for that whatsoever. Both implementations are valid, and they don't have to be identical. Even more, diversity is important, as it weeds out silly assumptions that are baked in non-portable SW. Windows doesn't boot? I won't loose any sleep over it. > > > However, we don't implement anything on the back of this instruction, > > so we just return NOT_IMPLEMENTED (-1). With NV, we actually use it as > > a guest hypervisor can use it for PSCI and SMC is guaranteed to trap > > even if EL3 doesn't exist in the HW. > > > > For the brain-damaged case where there is no EL3, SMC traps and the > > hypervisor doesn't actually advertises EL3, that's likely a guest > > bug. Tough luck. > > > > Side note: Not sure where HVF does, but on the M1 running Linux, SMC > > appears to trap to EL2 with EC=0x3f, which is a reserved exception > > class. This of course results in an UNDEF being injected because as > > far as KVM is concerned, this should never happen. > > Could that be yet another magical implementation specific MSR bit that > needs to be set? Hvf returns 0x17 (EC_AA64_SMC) for SMC calls. That's possible, but that's not something KVM will do. Also, from what I understand of HVF, this value is what you get in userspace, and it says nothing of what the kernel side does. It could well be translating the invalid EC into something else, after having read the instruction from the guest for all I know. It is pretty obvious that this HW is not a valid implementation of the architecture and if it decides to screw itself up, I'm happy to oblige. M. -- Without deviation from the norm, progress is not possible.