From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4E06C07E9D for ; Wed, 28 Sep 2022 01:47:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E257610E0A3; Wed, 28 Sep 2022 01:47:50 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8210510E037; Wed, 28 Sep 2022 01:47:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664329668; x=1695865668; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=xaMhUphfoNFBKjgL1NhfYiORn+hrOJbVG8Q9yRMOoDE=; b=dVa0ibDDpGg9pWLmDhXllZ522ilGkykj0N7WonrwMtEFLYXxUpSBvUbm /3dPUCfxVtblTDlGG07W1cs28nzpYVsSOVg/HLrPscpv8ZL4Qvl7o7GRH 6uoZ8N2n7hcU4pcmixIJbjdvC/3zuyV6Qi+Z3OWwzsf4RS+hEiIjZT3ya SbPAH99XT87wQUVu6pkVatWSnqUo7FrePEvCOnOMOT66o9Cb22cu2QDZf D8lmklmSkJ0CDlhf6ux+5EqcuJts3qDqAU7Nbn9KTlhRKyBUtLUgf/uH4 Tkhz18IdUQDGxDMDrU/ICFOrNis/hLkXC37SFsgiB/yRL/kb//sqCXlFX g==; X-IronPort-AV: E=McAfee;i="6500,9779,10483"; a="299076417" X-IronPort-AV: E=Sophos;i="5.93,350,1654585200"; d="scan'208";a="299076417" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2022 18:47:47 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10483"; a="710778107" X-IronPort-AV: E=Sophos;i="5.93,350,1654585200"; d="scan'208";a="710778107" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.13.135]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2022 18:47:28 -0700 Date: Tue, 27 Sep 2022 18:47:28 -0700 Message-ID: <87wn9o5ky7.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Badal Nilawar Subject: Re: [PATCH 1/1] drm/i915: Use GEN12 RPSTAT register In-Reply-To: <20220927113529.3646989-2-badal.nilawar@intel.com> References: <20220927113529.3646989-1-badal.nilawar@intel.com> <20220927113529.3646989-2-badal.nilawar@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andi.shyti@intel.com, donhiatt@gmail.com, tvrtko.ursulin@intel.com, anshuman.gupta@intel.com, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, jon.ewins@intel.com, vinay.belgaumkar@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, 27 Sep 2022 04:35:29 -0700, Badal Nilawar wrote: > > From: Don Hiatt > > On GEN12 and above use GEN12_RPSTAT register to get Current > Actual Graphics Frequency of GT I think even for the purposes of reviewing this it would be good to mention in the commit message that: a. GEN12_RPSTAT register doesn't require a forcewake to be read (it doesn't belong to a forcewake domain) b. Will result in a 0 frequency if the GT is in RC6 Thanks. -- Ashutosh > v2: > - Fixed review comments(Ashutosh) > - Added function intel_rps_read_rpstat_fw to read RPSTAT without > forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko) > > Cc: Don Hiatt > Cc: Andi Shyti > Signed-off-by: Don Hiatt > Signed-off-by: Badal Nilawar > --- > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 +++ > drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++-- > drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++ > drivers/gpu/drm/i915/i915_pmu.c | 3 +- > 5 files changed, 38 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > index 10f680dbd7b6..b9b47052b26d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > @@ -380,7 +380,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) > rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); > rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); > > - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); > + rpstat = intel_rps_read_rpstat(rps); > rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; > rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; > rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 7f79bbf97828..1f1e90acc1ab 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1519,6 +1519,10 @@ > #define VLV_RENDER_C0_COUNT _MMIO(0x138118) > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c) > > +#define GEN12_RPSTAT1 _MMIO(0x1381b4) > +#define GEN12_CAGF_SHIFT 11 > +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) > + > #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) > #define GEN11_CSME (31) > #define GEN11_GUNIT (28) > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 17b40b625e31..5a15a630b1c6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -2068,12 +2068,40 @@ void intel_rps_sanitize(struct intel_rps *rps) > rps_disable_interrupts(rps); > } > > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + if (GRAPHICS_VER(i915) >= 12) > + rpstat = GEN12_RPSTAT1; > + else > + rpstat = GEN6_RPSTAT1; > + > + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); > +} > + > +u32 intel_rps_read_rpstat(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + if (GRAPHICS_VER(i915) >= 12) > + rpstat = GEN12_RPSTAT1; > + else > + rpstat = GEN6_RPSTAT1; > + > + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); > +} > + > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 cagf; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > + if (GRAPHICS_VER(i915) >= 12) > + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > cagf = (rpstat >> 8) & 0xff; > else if (GRAPHICS_VER(i915) >= 9) > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; > @@ -2099,7 +2127,7 @@ static u32 read_cagf(struct intel_rps *rps) > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > vlv_punit_put(i915); > } else if (GRAPHICS_VER(i915) >= 6) { > - freq = intel_uncore_read(uncore, GEN6_RPSTAT1); > + freq = intel_rps_read_rpstat(rps); > } else { > freq = intel_uncore_read(uncore, MEMSTAT_ILK); > } > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h > index 4509dfdc52e0..76c8404d8416 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.h > +++ b/drivers/gpu/drm/i915/gt/intel_rps.h > @@ -47,6 +47,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); > u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); > u32 intel_rps_read_punit_req(struct intel_rps *rps); > u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); > +u32 intel_rps_read_rpstat(struct intel_rps *rps); > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); > void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); > void intel_rps_raise_unslice(struct intel_rps *rps); > void intel_rps_lower_unslice(struct intel_rps *rps); > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 958b37123bf1..67140a87182f 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -371,7 +371,6 @@ static void > frequency_sample(struct intel_gt *gt, unsigned int period_ns) > { > struct drm_i915_private *i915 = gt->i915; > - struct intel_uncore *uncore = gt->uncore; > struct i915_pmu *pmu = &i915->pmu; > struct intel_rps *rps = >->rps; > > @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) > * case we assume the system is running at the intended > * frequency. Fortunately, the read should rarely fail! > */ > - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1); > + val = intel_rps_read_rpstat_fw(rps); > if (val) > val = intel_rps_get_cagf(rps, val); > else > -- > 2.25.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19164C07E9D for ; Wed, 28 Sep 2022 01:47:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1F31D10E037; Wed, 28 Sep 2022 01:47:50 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8210510E037; Wed, 28 Sep 2022 01:47:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664329668; x=1695865668; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=xaMhUphfoNFBKjgL1NhfYiORn+hrOJbVG8Q9yRMOoDE=; b=dVa0ibDDpGg9pWLmDhXllZ522ilGkykj0N7WonrwMtEFLYXxUpSBvUbm /3dPUCfxVtblTDlGG07W1cs28nzpYVsSOVg/HLrPscpv8ZL4Qvl7o7GRH 6uoZ8N2n7hcU4pcmixIJbjdvC/3zuyV6Qi+Z3OWwzsf4RS+hEiIjZT3ya SbPAH99XT87wQUVu6pkVatWSnqUo7FrePEvCOnOMOT66o9Cb22cu2QDZf D8lmklmSkJ0CDlhf6ux+5EqcuJts3qDqAU7Nbn9KTlhRKyBUtLUgf/uH4 Tkhz18IdUQDGxDMDrU/ICFOrNis/hLkXC37SFsgiB/yRL/kb//sqCXlFX g==; X-IronPort-AV: E=McAfee;i="6500,9779,10483"; a="299076417" X-IronPort-AV: E=Sophos;i="5.93,350,1654585200"; d="scan'208";a="299076417" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2022 18:47:47 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10483"; a="710778107" X-IronPort-AV: E=Sophos;i="5.93,350,1654585200"; d="scan'208";a="710778107" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.13.135]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2022 18:47:28 -0700 Date: Tue, 27 Sep 2022 18:47:28 -0700 Message-ID: <87wn9o5ky7.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Badal Nilawar In-Reply-To: <20220927113529.3646989-2-badal.nilawar@intel.com> References: <20220927113529.3646989-1-badal.nilawar@intel.com> <20220927113529.3646989-2-badal.nilawar@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: Use GEN12 RPSTAT register X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andi.shyti@intel.com, donhiatt@gmail.com, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 27 Sep 2022 04:35:29 -0700, Badal Nilawar wrote: > > From: Don Hiatt > > On GEN12 and above use GEN12_RPSTAT register to get Current > Actual Graphics Frequency of GT I think even for the purposes of reviewing this it would be good to mention in the commit message that: a. GEN12_RPSTAT register doesn't require a forcewake to be read (it doesn't belong to a forcewake domain) b. Will result in a 0 frequency if the GT is in RC6 Thanks. -- Ashutosh > v2: > - Fixed review comments(Ashutosh) > - Added function intel_rps_read_rpstat_fw to read RPSTAT without > forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko) > > Cc: Don Hiatt > Cc: Andi Shyti > Signed-off-by: Don Hiatt > Signed-off-by: Badal Nilawar > --- > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 +++ > drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++-- > drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++ > drivers/gpu/drm/i915/i915_pmu.c | 3 +- > 5 files changed, 38 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > index 10f680dbd7b6..b9b47052b26d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > @@ -380,7 +380,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) > rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); > rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); > > - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); > + rpstat = intel_rps_read_rpstat(rps); > rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; > rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; > rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 7f79bbf97828..1f1e90acc1ab 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1519,6 +1519,10 @@ > #define VLV_RENDER_C0_COUNT _MMIO(0x138118) > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c) > > +#define GEN12_RPSTAT1 _MMIO(0x1381b4) > +#define GEN12_CAGF_SHIFT 11 > +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) > + > #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) > #define GEN11_CSME (31) > #define GEN11_GUNIT (28) > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 17b40b625e31..5a15a630b1c6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -2068,12 +2068,40 @@ void intel_rps_sanitize(struct intel_rps *rps) > rps_disable_interrupts(rps); > } > > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + if (GRAPHICS_VER(i915) >= 12) > + rpstat = GEN12_RPSTAT1; > + else > + rpstat = GEN6_RPSTAT1; > + > + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); > +} > + > +u32 intel_rps_read_rpstat(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + if (GRAPHICS_VER(i915) >= 12) > + rpstat = GEN12_RPSTAT1; > + else > + rpstat = GEN6_RPSTAT1; > + > + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); > +} > + > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 cagf; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > + if (GRAPHICS_VER(i915) >= 12) > + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > cagf = (rpstat >> 8) & 0xff; > else if (GRAPHICS_VER(i915) >= 9) > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; > @@ -2099,7 +2127,7 @@ static u32 read_cagf(struct intel_rps *rps) > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > vlv_punit_put(i915); > } else if (GRAPHICS_VER(i915) >= 6) { > - freq = intel_uncore_read(uncore, GEN6_RPSTAT1); > + freq = intel_rps_read_rpstat(rps); > } else { > freq = intel_uncore_read(uncore, MEMSTAT_ILK); > } > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h > index 4509dfdc52e0..76c8404d8416 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.h > +++ b/drivers/gpu/drm/i915/gt/intel_rps.h > @@ -47,6 +47,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); > u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); > u32 intel_rps_read_punit_req(struct intel_rps *rps); > u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); > +u32 intel_rps_read_rpstat(struct intel_rps *rps); > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); > void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); > void intel_rps_raise_unslice(struct intel_rps *rps); > void intel_rps_lower_unslice(struct intel_rps *rps); > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 958b37123bf1..67140a87182f 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -371,7 +371,6 @@ static void > frequency_sample(struct intel_gt *gt, unsigned int period_ns) > { > struct drm_i915_private *i915 = gt->i915; > - struct intel_uncore *uncore = gt->uncore; > struct i915_pmu *pmu = &i915->pmu; > struct intel_rps *rps = >->rps; > > @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) > * case we assume the system is running at the intended > * frequency. Fortunately, the read should rarely fail! > */ > - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1); > + val = intel_rps_read_rpstat_fw(rps); > if (val) > val = intel_rps_get_cagf(rps, val); > else > -- > 2.25.1 >