From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AD3CCCA47C for ; Sun, 26 Jun 2022 08:57:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234053AbiFZI5C (ORCPT ); Sun, 26 Jun 2022 04:57:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231126AbiFZI5A (ORCPT ); Sun, 26 Jun 2022 04:57:00 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAB0E11A21; Sun, 26 Jun 2022 01:56:59 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 97F4AB80D30; Sun, 26 Jun 2022 08:56:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 24FBAC341CA; Sun, 26 Jun 2022 08:56:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656233817; bh=Y02jfhJb1Aqml7DaR0aSSrkuFXXZPYf8YiFSNPaKI7s=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=eroUWlgUoQRbpFWysapxdXBVoUkOrEQpvFyG9hjANycmYhsy6EjgCPTMWsYIgsASa Urvby5om/JJ3V/EuSwdyynAGkJg8gO0keisYx0y32L6wLHj8fcyAPoFSduN7CyFUg1 h95354tLRMfOZcuvBSNlsy+u304toTu4ub3uk6tHAH4a9dFcAvz8LN9/6xX8UHgAUy BBAtpOPvGmXFuX/1R0EPyg/AA5Uurb3MgQalw0yNd1sbnkVgt/lG9dtz6rfZJPbLO8 /lyO/Jpm31W11yxjpijme6/kyUxwLK6ejIh4VQMyKx/aBrbSexfZlRXs24u7FaNWcz aWDaBHI1/I8xQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o5O4c-003Af3-TG; Sun, 26 Jun 2022 09:56:55 +0100 Date: Sun, 26 Jun 2022 09:57:00 +0100 Message-ID: <87wnd3erab.wl-maz@kernel.org> From: Marc Zyngier To: Lad Prabhakar Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC In-Reply-To: <20220626004326.8548-3-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220626004326.8548-3-prabhakar.mahadev-lad.rj@bp.renesas.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: prabhakar.mahadev-lad.rj@bp.renesas.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sagar.kadam@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, prabhakar.csengg@gmail.com, biju.das.jz@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 26 Jun 2022 01:43:26 +0100, Lad Prabhakar wrote: > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt > edge until the previous completion message has been received and > NCEPLIC100 doesn't support pending interrupt counter, hence losing the > interrupts if not acknowledged in time. > > So the workaround for edge-triggered interrupts to be handled correctly > and without losing is that it needs to be acknowledged first and then > handler must be run so that we don't miss on the next edge-triggered > interrupt. > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds > support to change interrupt flow based on the interrupt type. It also > implements irq_ack and irq_set_type callbacks. > > Signed-off-by: Lad Prabhakar > --- > v1->v2: > * Implemented IRQ flow as suggested by Marc > > RFC-->v1: > * Fixed review comments pointed by Geert > * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to > claim the interrupt by reading the register and then acknowledge it. > * Add a new chained handler for RZ/Five SoC. > --- > drivers/irqchip/Kconfig | 1 + > drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++- > 2 files changed, 72 insertions(+), 2 deletions(-) [...] > > +static int plic_irq_set_type(struct irq_data *d, unsigned int type) > +{ > + struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > + > + if (handler->priv->of_data != RENESAS_R9A07G043_PLIC) > + return 0; > + > + switch (type) { > + case IRQ_TYPE_LEVEL_HIGH: > + irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip, > + handle_fasteoi_ack_irq, > + "Edge"); > + break; > + > + case IRQ_TYPE_EDGE_RISING: > + irq_set_chip_handler_name_locked(d, &plic_chip, > + handle_fasteoi_irq, > + "Level"); > + break; Really? Have you even tested this? > + > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, > irq_hw_number_t hwirq) > { > @@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, > return 0; > } > > +static int plic_irq_domain_translate(struct irq_domain *d, > + struct irq_fwspec *fwspec, > + unsigned long *hwirq, > + unsigned int *type) > +{ > + struct plic_priv *priv = d->host_data; > + > + if (priv->of_data == RENESAS_R9A07G043_PLIC) > + return irq_domain_translate_twocell(d, fwspec, hwirq, type); > + > + return irq_domain_translate_onecell(d, fwspec, hwirq, type); > +} > + > static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, > unsigned int nr_irqs, void *arg) > { > @@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, > unsigned int type; > struct irq_fwspec *fwspec = arg; > > - ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); > + ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type); > if (ret) > return ret; > > @@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, > } > > static const struct irq_domain_ops plic_irqdomain_ops = { > - .translate = irq_domain_translate_onecell, > + .translate = plic_irq_domain_translate, > .alloc = plic_irq_domain_alloc, > .free = irq_domain_free_irqs_top, > }; > @@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node, > if (!priv) > return -ENOMEM; > > + if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) { > + priv->of_data = RENESAS_R9A07G043_PLIC; > + plic_chip.name = "Renesas RZ/Five PLIC"; NAK. The irq_chip structure isn't the place for platform marketing. This is way too long anyway (and same for the edge version), and you even sent me a patch to make that structure const... M. -- Without deviation from the norm, progress is not possible. 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Sun, 26 Jun 2022 09:56:55 +0100 Date: Sun, 26 Jun 2022 09:57:00 +0100 Message-ID: <87wnd3erab.wl-maz@kernel.org> From: Marc Zyngier To: Lad Prabhakar Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC In-Reply-To: <20220626004326.8548-3-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220626004326.8548-3-prabhakar.mahadev-lad.rj@bp.renesas.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: prabhakar.mahadev-lad.rj@bp.renesas.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sagar.kadam@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, prabhakar.csengg@gmail.com, biju.das.jz@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220626_015658_497237_490DF1DF X-CRM114-Status: GOOD ( 36.40 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, 26 Jun 2022 01:43:26 +0100, Lad Prabhakar wrote: > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt > edge until the previous completion message has been received and > NCEPLIC100 doesn't support pending interrupt counter, hence losing the > interrupts if not acknowledged in time. > > So the workaround for edge-triggered interrupts to be handled correctly > and without losing is that it needs to be acknowledged first and then > handler must be run so that we don't miss on the next edge-triggered > interrupt. > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds > support to change interrupt flow based on the interrupt type. It also > implements irq_ack and irq_set_type callbacks. > > Signed-off-by: Lad Prabhakar > --- > v1->v2: > * Implemented IRQ flow as suggested by Marc > > RFC-->v1: > * Fixed review comments pointed by Geert > * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to > claim the interrupt by reading the register and then acknowledge it. > * Add a new chained handler for RZ/Five SoC. > --- > drivers/irqchip/Kconfig | 1 + > drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++- > 2 files changed, 72 insertions(+), 2 deletions(-) [...] > > +static int plic_irq_set_type(struct irq_data *d, unsigned int type) > +{ > + struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > + > + if (handler->priv->of_data != RENESAS_R9A07G043_PLIC) > + return 0; > + > + switch (type) { > + case IRQ_TYPE_LEVEL_HIGH: > + irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip, > + handle_fasteoi_ack_irq, > + "Edge"); > + break; > + > + case IRQ_TYPE_EDGE_RISING: > + irq_set_chip_handler_name_locked(d, &plic_chip, > + handle_fasteoi_irq, > + "Level"); > + break; Really? Have you even tested this? > + > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, > irq_hw_number_t hwirq) > { > @@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, > return 0; > } > > +static int plic_irq_domain_translate(struct irq_domain *d, > + struct irq_fwspec *fwspec, > + unsigned long *hwirq, > + unsigned int *type) > +{ > + struct plic_priv *priv = d->host_data; > + > + if (priv->of_data == RENESAS_R9A07G043_PLIC) > + return irq_domain_translate_twocell(d, fwspec, hwirq, type); > + > + return irq_domain_translate_onecell(d, fwspec, hwirq, type); > +} > + > static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, > unsigned int nr_irqs, void *arg) > { > @@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, > unsigned int type; > struct irq_fwspec *fwspec = arg; > > - ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); > + ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type); > if (ret) > return ret; > > @@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, > } > > static const struct irq_domain_ops plic_irqdomain_ops = { > - .translate = irq_domain_translate_onecell, > + .translate = plic_irq_domain_translate, > .alloc = plic_irq_domain_alloc, > .free = irq_domain_free_irqs_top, > }; > @@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node, > if (!priv) > return -ENOMEM; > > + if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) { > + priv->of_data = RENESAS_R9A07G043_PLIC; > + plic_chip.name = "Renesas RZ/Five PLIC"; NAK. The irq_chip structure isn't the place for platform marketing. This is way too long anyway (and same for the edge version), and you even sent me a patch to make that structure const... M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv