From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C4A0C433F5 for ; Thu, 12 May 2022 07:38:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347461AbiELHis (ORCPT ); Thu, 12 May 2022 03:38:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351085AbiELHid (ORCPT ); Thu, 12 May 2022 03:38:33 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0B3635DE1; Thu, 12 May 2022 00:38:30 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 0BFD0CE2808; Thu, 12 May 2022 07:38:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 25A24C385B8; Thu, 12 May 2022 07:38:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652341107; bh=ugIyGV0pe1/xrkV0tlYgt/gRuv1slF9T3wv3KtmXcbg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=lfIcfEwPwHaF+77LvNlCFp1sc8z8jgmzhGnmwTNwPMCmO6Ra6PQd9IO6TUZm6DrMR 8ZUz+I+Gazc1Rfiei48ABujuX3aZDEX0jOfdXltvJyKm8o0GC/lAp71xSdDiq6Chhb UQeT0apxvc0fZAiYnYB1PaPWr5EWeB1P7i/vVOwmx1VSiR1uqncN8WnIwkGJNrkMz1 5P5XsF1AAnE4f3vWxj0LRRB0SWrN/PP3JgDxNNNcknK1X+Mc1EYNNoewwgtXR0OuCz GYFigyEMDhNif66CZM1RsFksozoiw/+jkstx8GkqZyM/8AT9lgUGNT979P72eNBW1Z tET4QDX7fSXcg== Received: from 82-132-234-237.dab.02.net ([82.132.234.237] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1np3Oy-00An74-HK; Thu, 12 May 2022 08:38:24 +0100 Date: Thu, 12 May 2022 08:38:23 +0100 Message-ID: <87wnermc9c.wl-maz@kernel.org> From: Marc Zyngier To: Chris Packham Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, kostap@marvell.com, robert.marko@sartura.hr, vadym.kochan@plvision.eu, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board In-Reply-To: <20220512042501.3339775-3-chris.packham@alliedtelesis.co.nz> References: <20220512042501.3339775-1-chris.packham@alliedtelesis.co.nz> <20220512042501.3339775-3-chris.packham@alliedtelesis.co.nz> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 82.132.234.237 X-SA-Exim-Rcpt-To: chris.packham@alliedtelesis.co.nz, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, kostap@marvell.com, robert.marko@sartura.hr, vadym.kochan@plvision.eu, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 12 May 2022 05:25:00 +0100, Chris Packham wrote: > > The 98DX2530 SoC is the Control and Management CPU integrated into > the Marvell 98DX25xx and 98DX35xx series of switch chip (internally > referred to as AlleyCat5 and AlleyCat5X). > > These files have been taken from the Marvell SDK and lightly cleaned > up with the License and copyright retained. > > Signed-off-by: Chris Packham > Reviewed-by: Andrew Lunn > --- > > Notes: > The Marvell SDK has a number of new compatible strings. I've brought > through some of the drivers or where possible used an in-tree > alternative (e.g. there is SDK code for a ac5-gpio but two instances of > the existing marvell,orion-gpio seems to cover what is needed if you use > an appropriate binding). I expect that there will a new series of > patches when I get some different hardware (or additions to this series > depending on if/when it lands). > > Changes in v7: > - Add missing compatible on usb1 > - Add "rd-ac5x" compatible for board > - Move aliases to board dts > - Move board specific usb info to board dts > - Consolidate usb1 board settings and remove unnecessary compatible > - Add Allied Telesis copyright > - Rename files after mailng-list discussion > Changes in v6: > - Move CPU nodes above the SoC (Krzysztof) > - Minor formatting clean ups (Krzysztof) > - Run through `make dtbs_check` > - Move gic nodes inside SoC > - Group clocks under a clock node > Changes in v5: > - add #{address,size}-cells property to i2c nodes > - make i2c nodes disabled in the SoC and enable them in the board > - add interrupt controller attributes to gpio nodes > - Move fixed-clock nodes up a level and remove unnecessary @0 > Changes in v4: > - use 'phy-handle' instead of 'phy' > - move status="okay" on usb nodes to board dts > - Add review from Andrew > Changes in v3: > - Move memory node to board > - Use single digit reg value for phy address > - Remove MMC node (driver needs work) > - Remove syscon & simple-mfd for pinctrl > Changes in v2: > - Make pinctrl a child node of a syscon node > - Use marvell,armada-8k-gpio instead of orion-gpio > - Remove nand peripheral. The Marvell SDK does have some changes for the > ac5-nand-controller but I currently lack hardware with NAND fitted so > I can't test it right now. I've therefore chosen to omit the node and > not attempted to bring in the driver or binding. > - Remove pcie peripheral. Again there are changes in the SDK and I have > no way of testing them. > - Remove prestera node. > - Remove "marvell,ac5-ehci" compatible from USB node as > "marvell,orion-ehci" is sufficient > - Remove watchdog node. There is a buggy driver for the ac5 watchdog in > the SDK but it needs some work so I've dropped the node for now. > > arch/arm64/boot/dts/marvell/Makefile | 1 + > .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ > .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ > .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + > 4 files changed, 410 insertions(+) > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi > > diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile > index 1c794cdcb8e6..b7a4c715afbb 100644 > --- a/arch/arm64/boot/dts/marvell/Makefile > +++ b/arch/arm64/boot/dts/marvell/Makefile > @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb > +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb > diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > new file mode 100644 > index 000000000000..55ab4cd843a9 > --- /dev/null > +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > @@ -0,0 +1,295 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Device Tree For AC5. > + * > + * Copyright (C) 2021 Marvell > + * Copyright (C) 2022 Allied Telesis Labs > + */ > + > +#include > +#include > + > +/ { > + model = "Marvell AC5 SoC"; > + compatible = "marvell,ac5"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache { > + compatible = "cache"; > + }; > + }; > + > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + clock-frequency = <25000000>; I said no to this hack in a past version of this patch, and I'm going to say it *again*. Please fix your firmware to program CNTFRQ_EL0, and remove this useless property. You are also missing a PPI for the EL2 virtual timer which is present on any ARMv8.1+ CPU (and since this system is using A55, it definitely has it). [...] > + > + gic: interrupt-controller@80600000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + /*#redistributor-regions = <1>;*/ > + redistributor-stride = <0x0 0x20000>; // 128kB stride You don't need this at all. This is the architected value for GICv3. > + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ > + <0x0 0x80660000 0x0 0x40000>; /* GICR */ > + interrupts = ; > + }; > + }; Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBA3AC433EF for ; Thu, 12 May 2022 07:39:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5bXEi7PlIsvWbPKGMMjXHRvSHkA/kwYOGveIO2PPHE0=; b=YEqyRmrt8Q+muP PcagJSoysOEDVQPfZ9x73xsH/tfE5EVVYSE+b76oVwTRKowYc1PRZtvyvR4JMOjwra9zsL0OR8fLY r8s8n4bHgnqVbqYJXH+Cc9nx2KKWuaDaJwQlWPJl5EOg3DPEcZU1KyMRbEUptk0DwASyVQbt00kzv xkC1qtw2hpldLx9oX4YpyXQv3tI4ONX7W2Fkv4Qg3UQe6EevTM39P2//x4gysmF5HoipSWIm8Tz8M AeeTy6TgOP6U0ijwrAmxpjKprWqkR/83cV+xdOJ1S/ja8wXYEj6+X2UB91S/U50cAGcIaZXxLAnxQ PXB3f/Rn9d9l20s9EUdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1np3P6-00AmZ5-Ih; Thu, 12 May 2022 07:38:32 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1np3P3-00AmXf-AH for linux-arm-kernel@lists.infradead.org; Thu, 12 May 2022 07:38:31 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 253B561EC3; Thu, 12 May 2022 07:38:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 25A24C385B8; Thu, 12 May 2022 07:38:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652341107; bh=ugIyGV0pe1/xrkV0tlYgt/gRuv1slF9T3wv3KtmXcbg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=lfIcfEwPwHaF+77LvNlCFp1sc8z8jgmzhGnmwTNwPMCmO6Ra6PQd9IO6TUZm6DrMR 8ZUz+I+Gazc1Rfiei48ABujuX3aZDEX0jOfdXltvJyKm8o0GC/lAp71xSdDiq6Chhb UQeT0apxvc0fZAiYnYB1PaPWr5EWeB1P7i/vVOwmx1VSiR1uqncN8WnIwkGJNrkMz1 5P5XsF1AAnE4f3vWxj0LRRB0SWrN/PP3JgDxNNNcknK1X+Mc1EYNNoewwgtXR0OuCz GYFigyEMDhNif66CZM1RsFksozoiw/+jkstx8GkqZyM/8AT9lgUGNT979P72eNBW1Z tET4QDX7fSXcg== Received: from 82-132-234-237.dab.02.net ([82.132.234.237] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1np3Oy-00An74-HK; Thu, 12 May 2022 08:38:24 +0100 Date: Thu, 12 May 2022 08:38:23 +0100 Message-ID: <87wnermc9c.wl-maz@kernel.org> From: Marc Zyngier To: Chris Packham Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, kostap@marvell.com, robert.marko@sartura.hr, vadym.kochan@plvision.eu, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board In-Reply-To: <20220512042501.3339775-3-chris.packham@alliedtelesis.co.nz> References: <20220512042501.3339775-1-chris.packham@alliedtelesis.co.nz> <20220512042501.3339775-3-chris.packham@alliedtelesis.co.nz> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 82.132.234.237 X-SA-Exim-Rcpt-To: chris.packham@alliedtelesis.co.nz, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, kostap@marvell.com, robert.marko@sartura.hr, vadym.kochan@plvision.eu, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220512_003829_473708_DD497B14 X-CRM114-Status: GOOD ( 46.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 12 May 2022 05:25:00 +0100, Chris Packham wrote: > > The 98DX2530 SoC is the Control and Management CPU integrated into > the Marvell 98DX25xx and 98DX35xx series of switch chip (internally > referred to as AlleyCat5 and AlleyCat5X). > > These files have been taken from the Marvell SDK and lightly cleaned > up with the License and copyright retained. > > Signed-off-by: Chris Packham > Reviewed-by: Andrew Lunn > --- > > Notes: > The Marvell SDK has a number of new compatible strings. I've brought > through some of the drivers or where possible used an in-tree > alternative (e.g. there is SDK code for a ac5-gpio but two instances of > the existing marvell,orion-gpio seems to cover what is needed if you use > an appropriate binding). I expect that there will a new series of > patches when I get some different hardware (or additions to this series > depending on if/when it lands). > > Changes in v7: > - Add missing compatible on usb1 > - Add "rd-ac5x" compatible for board > - Move aliases to board dts > - Move board specific usb info to board dts > - Consolidate usb1 board settings and remove unnecessary compatible > - Add Allied Telesis copyright > - Rename files after mailng-list discussion > Changes in v6: > - Move CPU nodes above the SoC (Krzysztof) > - Minor formatting clean ups (Krzysztof) > - Run through `make dtbs_check` > - Move gic nodes inside SoC > - Group clocks under a clock node > Changes in v5: > - add #{address,size}-cells property to i2c nodes > - make i2c nodes disabled in the SoC and enable them in the board > - add interrupt controller attributes to gpio nodes > - Move fixed-clock nodes up a level and remove unnecessary @0 > Changes in v4: > - use 'phy-handle' instead of 'phy' > - move status="okay" on usb nodes to board dts > - Add review from Andrew > Changes in v3: > - Move memory node to board > - Use single digit reg value for phy address > - Remove MMC node (driver needs work) > - Remove syscon & simple-mfd for pinctrl > Changes in v2: > - Make pinctrl a child node of a syscon node > - Use marvell,armada-8k-gpio instead of orion-gpio > - Remove nand peripheral. The Marvell SDK does have some changes for the > ac5-nand-controller but I currently lack hardware with NAND fitted so > I can't test it right now. I've therefore chosen to omit the node and > not attempted to bring in the driver or binding. > - Remove pcie peripheral. Again there are changes in the SDK and I have > no way of testing them. > - Remove prestera node. > - Remove "marvell,ac5-ehci" compatible from USB node as > "marvell,orion-ehci" is sufficient > - Remove watchdog node. There is a buggy driver for the ac5 watchdog in > the SDK but it needs some work so I've dropped the node for now. > > arch/arm64/boot/dts/marvell/Makefile | 1 + > .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ > .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ > .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + > 4 files changed, 410 insertions(+) > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi > > diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile > index 1c794cdcb8e6..b7a4c715afbb 100644 > --- a/arch/arm64/boot/dts/marvell/Makefile > +++ b/arch/arm64/boot/dts/marvell/Makefile > @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb > +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb > diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > new file mode 100644 > index 000000000000..55ab4cd843a9 > --- /dev/null > +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > @@ -0,0 +1,295 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Device Tree For AC5. > + * > + * Copyright (C) 2021 Marvell > + * Copyright (C) 2022 Allied Telesis Labs > + */ > + > +#include > +#include > + > +/ { > + model = "Marvell AC5 SoC"; > + compatible = "marvell,ac5"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache { > + compatible = "cache"; > + }; > + }; > + > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + clock-frequency = <25000000>; I said no to this hack in a past version of this patch, and I'm going to say it *again*. Please fix your firmware to program CNTFRQ_EL0, and remove this useless property. You are also missing a PPI for the EL2 virtual timer which is present on any ARMv8.1+ CPU (and since this system is using A55, it definitely has it). [...] > + > + gic: interrupt-controller@80600000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + /*#redistributor-regions = <1>;*/ > + redistributor-stride = <0x0 0x20000>; // 128kB stride You don't need this at all. This is the architected value for GICv3. > + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ > + <0x0 0x80660000 0x0 0x40000>; /* GICR */ > + interrupts = ; > + }; > + }; Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel