From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C9E7C433F5 for ; Wed, 20 Apr 2022 05:54:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF7DB10F0D5; Wed, 20 Apr 2022 05:54:46 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id AC95210F0C2 for ; Wed, 20 Apr 2022 05:54:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1650434085; x=1681970085; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=dhoMzdkf65Iyc+8jHvPOfDC+zKcYLcOivwMh2RoUT1A=; b=JILlsICmO448SOOHLAZEWRBjCQjqqd6HEXtMPoocCrqZS3/Khmvnw2cn QtEfZZWDz890W9FhnFvxzyPXURYFxSinaB00K/0lrA/paKj8jbrXaRsLz qapHr3SikR860qPXVvMPHU58cZoHlavoG7BHN2f3ZH2lMipIwA6GlUYLw +7So/NzJoVCeZj2gOH8D8VKm8C5nz/1qTK5m3lzTV4NKId3fN+0pvcZ5r a0ngFHC/t9oILWRLUY8Dc21SoHCe8Df9leve42aX7PWvAbjntvQkTilNS c0kLaCu4rMzBjBvTRtIVvNZ7j/TS3qcJUX8mBYQ0SPquZsfdFKGoyX/LB A==; X-IronPort-AV: E=McAfee;i="6400,9594,10322"; a="289050474" X-IronPort-AV: E=Sophos;i="5.90,274,1643702400"; d="scan'208";a="289050474" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2022 22:54:44 -0700 X-IronPort-AV: E=Sophos;i="5.90,274,1643702400"; d="scan'208";a="576434227" Received: from adixit-mobl1.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.210.49]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2022 22:54:44 -0700 Date: Tue, 19 Apr 2022 22:54:44 -0700 Message-ID: <87wnfkwb8b.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Rodrigo Vivi In-Reply-To: References: <8f667da9aa39452524abef1333226b645438d2cc.1649871650.git.ashutosh.dixit@intel.com> <87lew7eque.fsf@intel.com> <878rs72t78.wl-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/pcode: Extend pcode functions for multiple gt's X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 15 Apr 2022 03:21:26 -0700, Rodrigo Vivi wrote: > On Thu, Apr 14, 2022 at 03:31:07PM -0700, Dixit, Ashutosh wrote: > > On Thu, 14 Apr 2022 06:28:57 -0700, Jani Nikula wrote: > > > > > > On Wed, 13 Apr 2022, Ashutosh Dixit wrote: > > > > Each gt contains an independent instance of pcode. Extend pcode functions > > > > to interface with pcode on different gt's. Previous (GT0) pcode read/write > > > > interfaces are preserved. > > > > > > The big problem here is that this hard couples display code to gt code, > > > while we're trying hard to go the opposite direction. It doesn't matter > > > that the existing interfaces are preserved as wrappers when it relies on > > > an intel_gt being available (via i915->gt0). > > I don't believe there is a big problem in here... > > please note the intel_pcode.h is keeping the abstraction for display > > #define snb_pcode_write_timeout(i915, mbox, val, fast_timeout_us, slow_timeout_ms) \ > intel_gt_pcode_write_timeout(&(i915)->gt0, mbox, val, fast_timeout_us, slow_timeout_ms) > > #define snb_pcode_write(i915, mbox, val) \ > snb_pcode_write_timeout(i915, mbox, val, 500, 0) > > display only uses these macros that Ashutosh didn't touch. > > > > > > > Note how 'git grep intel_gt -- drivers/gpu/drm/i915/display/' matches > > > only 1 line. > > As well with the patches applied: > > $ git log --oneline -1 > 1f58f1195478 (HEAD -> drm-tip) drm/i915/gt: Expose per-gt RPS defaults in sysfs > > $ git grep intel_gt -- drivers/gpu/drm/i915/display/ > drivers/gpu/drm/i915/display/intel_display.c: intel_gt_set_wedged(to_gt(dev_priv)); > > > > > Hi Jani, would you have suggestions about how to do this (handle pcode on > > multiple gt's)? The thinking was this patch would be a straightforward way > > to avoid code duplication. Also: > > Maybe it is just a matter of renaming the macros used by display > in intel_pcode.h to reflect that it should be used by display only? In v2 I have added a patch ([PATCH 4/9] drm/i915/gt: Convert callers to user per-gt pcode functions) which correctly calls per-gt pcode functions where this is required. With this patch only display functions (and one other caller) are left calling the "global scope" snb_pcode_read/write* functions. So the legacy snb_pcode_read/write* are now basically being used only by display. Let's see if Jani is ok with this. Thanks.