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Wed, 2 Feb 2022 14:12:55 +0000 (GMT) References: <20211218194250.247633-1-richard.henderson@linaro.org> <20211218194250.247633-12-richard.henderson@linaro.org> User-agent: mu4e 1.7.6; emacs 28.0.91 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Subject: Re: [PATCH 11/20] tcg/i386: Implement avx512 immediate rotate Date: Wed, 02 Feb 2022 14:05:24 +0000 In-reply-to: <20211218194250.247633-12-richard.henderson@linaro.org> Message-ID: <87wniduzko.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::535 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > AVX512VL has VPROLD and VPROLQ, layered onto the same > opcode as PSHIFTD, but requires EVEX encoding and W. > > Signed-off-by: Richard Henderson > --- > tcg/i386/tcg-target.h | 2 +- > tcg/i386/tcg-target.c.inc | 15 +++++++++++++-- > 2 files changed, 14 insertions(+), 3 deletions(-) > > diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h > index 12d098ad6c..38c09fd66c 100644 > --- a/tcg/i386/tcg-target.h > +++ b/tcg/i386/tcg-target.h > @@ -195,7 +195,7 @@ extern bool have_movbe; > #define TCG_TARGET_HAS_not_vec 0 > #define TCG_TARGET_HAS_neg_vec 0 > #define TCG_TARGET_HAS_abs_vec 1 > -#define TCG_TARGET_HAS_roti_vec 0 > +#define TCG_TARGET_HAS_roti_vec have_avx512vl > #define TCG_TARGET_HAS_rots_vec 0 > #define TCG_TARGET_HAS_rotv_vec 0 > #define TCG_TARGET_HAS_shi_vec 1 > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index c4e6f2e5ea..5ab7c4c0fa 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -361,7 +361,7 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) > #define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2) > #define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3) > #define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ > -#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */ > +#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /1 /2 /6 /4 */ > #define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ > #define OPC_PSLLW (0xf1 | P_EXT | P_DATA16) > #define OPC_PSLLD (0xf2 | P_EXT | P_DATA16) > @@ -2906,6 +2906,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcod= e opc, > insn |=3D P_VEXW | P_EVEX; > } > sub =3D 4; > + goto gen_shift; > + case INDEX_op_rotli_vec: > + insn =3D OPC_PSHIFTD_Ib | P_EVEX; /* VPROL[DQ] */ > + if (vece =3D=3D MO_64) { > + insn |=3D P_VEXW; > + } > + sub =3D 1; > + goto gen_shift; This could just be a /* fall-through */ although given the large amount of gotos the switch statement is gathering I'm not sure it makes too much difference. Is there any reason why gen_shift couldn't be pushed into a helper function so we just had: static void tcg_out_vec_shift(s, vece, insn, sub, a0, a1, a2) { tcg_debug_assert(vece !=3D MO_8); if (type =3D=3D TCG_TYPE_V256) { insn |=3D P_VEXL; } tcg_out_vex_modrm(s, insn, sub, a0, a1); tcg_out8(s, a2); } ... case INDEX_op_rotli_vec: insn =3D OPC_PSHIFTD_Ib | P_EVEX; /* VPROL[DQ] */ if (vece =3D=3D MO_64) { insn |=3D P_VEXW; } tcg_out_vec_shift(s, vece, insn, 1, a0, a1, a2); break; Surely the compiler would inline if needed (and even if it didn't it the code generation that critical we care about a few cycles)? --=20 Alex Benn=C3=A9e