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From:   Thomas Gleixner <tglx@linutronix.de>
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To:     "Rafael J. Wysocki" <rafael@kernel.org>,
        Deepak Sharma <deepak.sharma@amd.com>
Cc:     "Rafael J. Wysocki" <rafael@kernel.org>,
        Len Brown <len.brown@intel.com>, Pavel Machek <pavel@ucw.cz>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        the arch/x86 maintainers <x86@kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux PM <linux-pm@vger.kernel.org>
Subject: Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs
In-Reply-To: <CAJZ5v0iS+TnkoqCxLa92Na=By53PXY-qW=k4utr_84KYaw+sVQ@mail.gmail.com>
References: <20210924061205.5523-1-deepak.sharma@amd.com>
 <CAJZ5v0iS+TnkoqCxLa92Na=By53PXY-qW=k4utr_84KYaw+sVQ@mail.gmail.com>
Date:   Sun, 26 Sep 2021 17:12:59 +0200
Message-ID: <87wnn3bcas.ffs@tglx>
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On Fri, Sep 24 2021 at 18:48, Rafael J. Wysocki wrote:

> On Fri, Sep 24, 2021 at 8:12 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
>>
>> All Zen or newer CPU which support C3 shares cache. Its not necessary to
>> flush the caches in software before entering C3. This will cause drop in
>> performance for the cores which share some caches. ARB_DIS is not used
>> with current AMD C state implementation. So set related flags correctly.
>>
>> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
>
> I'm planning to take this one unless the x86 maintainers have concerns, thanks.

Acked-by: Thomas Gleixner <tglx@linutronix.de>