From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: From: Gregory CLEMENT In-Reply-To: <75637257694de0d4a9e432e1d8270019a4e6328b.1610364681.git.baruch@tkos.co.il> References: <75637257694de0d4a9e432e1d8270019a4e6328b.1610364681.git.baruch@tkos.co.il> Date: Fri, 29 Jan 2021 16:55:10 +0100 Message-ID: <87wnvvsppd.fsf@BL-laptop> MIME-Version: 1.0 Content-Type: text/plain Subject: Re: [PATCH v7 2/3] arm64: dts: armada: add pwm offsets for ap/cp gpios To: Baruch Siach , Thierry Reding , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Lee Jones , Linus Walleij , Bartosz Golaszewski , Rob Herring Cc: Baruch Siach , Andrew Lunn , Russell King , Sebastian Hesselbarth , Thomas Petazzoni , Chris Packham , Sascha Hauer , Ralph Sennhauser , linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org List-ID: Hi Baruch, > The 'marvell,pwm-offset' property of both GPIO blocks (per CP component) > point to the same counter registers offset. The driver will decide how > to use counters A/B. > > This is different from the convention of pwm on earlier Armada series > (370/38x). On those systems the assignment of A/B counters to GPIO > blocks is coded in both DT and the driver. The actual behaviour of the > current driver on Armada 8K/7K is the same as earlier systems. > > Add also clock properties for base pwm frequency reference. > > Signed-off-by: Baruch Siach Applied on mvebu/dt64 Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 3 +++ > arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > index 12e477f1aeb9..6614472100c2 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > @@ -281,6 +281,9 @@ ap_gpio: gpio@1040 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&ap_pinctrl 0 0 20>; > + marvell,pwm-offset = <0x10c0>; > + #pwm-cells = <2>; > + clocks = <&ap_clk 3>; > }; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi > index 994a2fce449a..d774a39334d9 100644 > --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi > @@ -234,12 +234,17 @@ CP11X_LABEL(gpio1): gpio@100 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, > <85 IRQ_TYPE_LEVEL_HIGH>, > <84 IRQ_TYPE_LEVEL_HIGH>, > <83 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(clk) 1 21>, > + <&CP11X_LABEL(clk) 1 17>; > status = "disabled"; > }; > > @@ -250,12 +255,17 @@ CP11X_LABEL(gpio2): gpio@140 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, > <81 IRQ_TYPE_LEVEL_HIGH>, > <80 IRQ_TYPE_LEVEL_HIGH>, > <79 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(clk) 1 21>, > + <&CP11X_LABEL(clk) 1 17>; > status = "disabled"; > }; > }; > -- > 2.29.2 > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8075DC433E0 for ; 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Fri, 29 Jan 2021 15:55:10 +0000 (UTC) From: Gregory CLEMENT To: Baruch Siach , Thierry Reding , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Lee Jones , Linus Walleij , Bartosz Golaszewski , Rob Herring Subject: Re: [PATCH v7 2/3] arm64: dts: armada: add pwm offsets for ap/cp gpios In-Reply-To: <75637257694de0d4a9e432e1d8270019a4e6328b.1610364681.git.baruch@tkos.co.il> References: <75637257694de0d4a9e432e1d8270019a4e6328b.1610364681.git.baruch@tkos.co.il> Date: Fri, 29 Jan 2021 16:55:10 +0100 Message-ID: <87wnvvsppd.fsf@BL-laptop> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210129_105515_601241_DD2DDA4A X-CRM114-Status: GOOD ( 17.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Baruch Siach , linux-pwm@vger.kernel.org, Sascha Hauer , Russell King , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Chris Packham , Thomas Petazzoni , Ralph Sennhauser , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Baruch, > The 'marvell,pwm-offset' property of both GPIO blocks (per CP component) > point to the same counter registers offset. The driver will decide how > to use counters A/B. > > This is different from the convention of pwm on earlier Armada series > (370/38x). On those systems the assignment of A/B counters to GPIO > blocks is coded in both DT and the driver. The actual behaviour of the > current driver on Armada 8K/7K is the same as earlier systems. > > Add also clock properties for base pwm frequency reference. > > Signed-off-by: Baruch Siach Applied on mvebu/dt64 Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 3 +++ > arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > index 12e477f1aeb9..6614472100c2 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > @@ -281,6 +281,9 @@ ap_gpio: gpio@1040 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&ap_pinctrl 0 0 20>; > + marvell,pwm-offset = <0x10c0>; > + #pwm-cells = <2>; > + clocks = <&ap_clk 3>; > }; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi > index 994a2fce449a..d774a39334d9 100644 > --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi > @@ -234,12 +234,17 @@ CP11X_LABEL(gpio1): gpio@100 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, > <85 IRQ_TYPE_LEVEL_HIGH>, > <84 IRQ_TYPE_LEVEL_HIGH>, > <83 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(clk) 1 21>, > + <&CP11X_LABEL(clk) 1 17>; > status = "disabled"; > }; > > @@ -250,12 +255,17 @@ CP11X_LABEL(gpio2): gpio@140 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, > <81 IRQ_TYPE_LEVEL_HIGH>, > <80 IRQ_TYPE_LEVEL_HIGH>, > <79 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(clk) 1 21>, > + <&CP11X_LABEL(clk) 1 17>; > status = "disabled"; > }; > }; > -- > 2.29.2 > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel