From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35826) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bgamm-0001ZN-Hh for qemu-devel@nongnu.org; Sun, 04 Sep 2016 13:00:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bgami-0006ED-DM for qemu-devel@nongnu.org; Sun, 04 Sep 2016 13:00:47 -0400 Received: from mail-wm0-x236.google.com ([2a00:1450:400c:c09::236]:36984) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bgamh-0006E8-R1 for qemu-devel@nongnu.org; Sun, 04 Sep 2016 13:00:44 -0400 Received: by mail-wm0-x236.google.com with SMTP id w12so4365310wmf.0 for ; Sun, 04 Sep 2016 10:00:42 -0700 (PDT) References: <1472797976-24210-1-git-send-email-nikunj@linux.vnet.ibm.com> <1472797976-24210-5-git-send-email-nikunj@linux.vnet.ibm.com> <1472800972.9620.8.camel@kernel.crashing.org> <87y43akb51.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <87y43akb51.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> Date: Sun, 04 Sep 2016 18:00:40 +0100 Message-ID: <87wpirbnwn.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH RFC 4/4] target-ppc: flush tlb from all the cpu List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: Benjamin Herrenschmidt , qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, qemu-devel@nongnu.org Nikunj A Dadhania writes: > Benjamin Herrenschmidt writes: > >> On Fri, 2016-09-02 at 12:02 +0530, Nikunj A Dadhania wrote: >>> Signed-off-by: Nikunj A Dadhania >>> --- >>> cputlb.c| 15 +++++++++++++++ >>> include/exec/exec-all.h |2 ++ >>> target-ppc/mmu-hash64.c |2 +- >>> 3 files changed, 18 insertions(+), 1 deletion(-) >>> >>> diff --git a/cputlb.c b/cputlb.c >>> index 64faf47..17ff58e 100644 >>> --- a/cputlb.c >>> +++ b/cputlb.c >>> @@ -123,6 +123,21 @@ void tlb_flush(CPUState *cpu, int flush_global) >>> } >>> } >>> >>> +static void tlb_flush_all_async_work(CPUState *cpu, void *opaque) >>> +{ >>> +tlb_flush_nocheck(cpu, GPOINTER_TO_INT(opaque)); >>> +} >>> + >>> +void tlb_flush_all(CPUState *cpu, int flush_global) >>> +{ >>> +CPUState *c; >>> + >>> +CPU_FOREACH(c) { >>> +async_run_on_cpu(c, tlb_flush_all_async_work, >>> +GUINT_TO_POINTER(flush_global)); >>> +} >>> +} >> >> Hrm... this is asynchronous? > > Yes. > >> It probably needs to be synchronous... > > I see run_on_cpu() which seems suitable. I'm not so happy with run_on_cpu as it involves busy waiting for the other CPU to finish. >> We must provide a guarantee that no other processor can see the old >> translation when the tlb invalidation sequence completes. With the >> current lazy TLB flush, we already delay the invalidation until >> we hit that synchronization point so we need to be synchronous. When is the synchronisation point? On ARM we end the basic block on system instructions that mess with the cache. As a result the flush is done as soon as we exit the run loop on the next instruction. > > >>> diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c >>> index 8118143..d852c21 100644 >>> --- a/target-ppc/mmu-hash64.c >>> +++ b/target-ppc/mmu-hash64.c >>> @@ -912,7 +912,7 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, >>> * invalidate, and we still don't have a tlb_flush_mask(env, n, >>> * mask) in QEMU, we just invalidate all TLBs >>> */ >>> -tlb_flush(CPU(cpu), 1); >>> +tlb_flush_all(CPU(cpu), 1); >>> } >>> >>> void ppc_hash64_update_rmls(CPUPPCState *env) > > Regards, > Nikunj -- Alex Bennée