From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16B3EC6FA82 for ; Mon, 26 Sep 2022 16:07:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A8F610E71B; Mon, 26 Sep 2022 16:07:29 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 647DA10E72B for ; Mon, 26 Sep 2022 16:07:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664208445; x=1695744445; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=cO3v7yp/SDmumPf+s/JKLXtZXM/apQzDXS25tMdAU9Y=; b=T/8uTaikshidu9rI0xOtIOgEUTcSU6HCsw9d5oNXHFUgmwFLJQoiy0/Q XVFZBADW6SuMV6wEhzZvPsgm0NrWTSWDbu3CQbORoxLEIREdjmtkoKUCL PkTOuK7OzIlbKZmalz/iqV+dk0gF09om8cyu07S9CQL5QSlc1bT7cGFmg OewlxqEwtZNeJsBzkIPt8p+g9LnDAwZHzkSEkkE76D9xclmHFlliBEczv zNRFvDFiPHzSGygkVvxqW3vHgBQ1y2ndsWP/Fi2cu0vQTRNLSiHA8xf0B 3U0/jvF5DqDLMyYrtDbhVCQNIsEOPUnLK70NyWyWxbOm1tnO/H1W3BJlY w==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="365099882" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="365099882" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 09:06:29 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="710172417" X-IronPort-AV: E=Sophos;i="5.93,346,1654585200"; d="scan'208";a="710172417" Received: from justinbl-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.181.227]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 09:06:28 -0700 Date: Mon, 26 Sep 2022 08:56:01 -0700 Message-ID: <87y1u6uo32.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20220923201154.283784-15-umesh.nerlige.ramappa@intel.com> References: <20220923201154.283784-1-umesh.nerlige.ramappa@intel.com> <20220923201154.283784-15-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH v2 14/15] drm/i915/guc: Support OA when Wa_16011777198 is enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 23 Sep 2022 13:11:53 -0700, Umesh Nerlige Ramappa wrote: > > From: Vinay Belgaumkar Hi Umesh/Vinay, > @@ -3254,6 +3265,24 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, > intel_engine_pm_get(stream->engine); > intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL); > > + /* > + * Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes > + * OA to lose the configuration state. Prevent this by overriding GUCRC > + * mode. > + */ > + if (intel_guc_slpc_is_used(>->uc.guc) && > + intel_uc_uses_guc_rc(>->uc) && Is this condition above correct? E.g. what happens when: a. GuCRC is used but SLPC is not used? b. GuCRC is not used. Don't we need to disable RC6 in host based RC6 control? Do we need to worry about these cases? Or if we always expect both GuCRC and SLPC to be used on DG2 then I think let's get rid of these from the if condition and add a drm_err() if we see these not being used and OA is being enabled on DG2? Thanks. -- Ashutosh > + (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || > + IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) { > + ret = intel_guc_slpc_override_gucrc_mode(>->uc.guc.slpc, > + SLPC_GUCRC_MODE_GUCRC_NO_RC6); > + if (ret) { > + drm_dbg(&stream->perf->i915->drm, > + "Unable to override gucrc mode\n"); > + goto err_config; > + } > + } > + > ret = alloc_oa_buffer(stream); > if (ret) > goto err_oa_buf_alloc; > -- > 2.25.1 >