From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA939C433FE for ; Wed, 20 Oct 2021 16:49:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9214F6137C for ; Wed, 20 Oct 2021 16:49:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230385AbhJTQvR (ORCPT ); Wed, 20 Oct 2021 12:51:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:44932 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230130AbhJTQuz (ORCPT ); Wed, 20 Oct 2021 12:50:55 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 819186137C; Wed, 20 Oct 2021 16:48:41 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mdElb-000U2P-6W; Wed, 20 Oct 2021 17:48:39 +0100 Date: Wed, 20 Oct 2021 17:48:38 +0100 Message-ID: <87y26nbq1l.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Guo Ren , Samuel Holland , Atish Patra , Thomas Gleixner , Palmer Dabbelt , Heiko =?UTF-8?B?U3TDvGJuZXI=?= , Rob Herring , Linux Kernel Mailing List , linux-riscv , Guo Ren Subject: Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support In-Reply-To: References: <20211016032200.2869998-1-guoren@kernel.org> <20211016032200.2869998-2-guoren@kernel.org> <8be1bdbd-365d-cd28-79d7-b924908f9e39@sholland.org> <8735oxuxlq.wl-maz@kernel.org> <875ytrddma.wl-maz@kernel.org> <871r4fd996.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anup@brainfault.org, guoren@kernel.org, samuel@sholland.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 20 Oct 2021 17:08:36 +0100, Anup Patel wrote: > > On Wed, Oct 20, 2021 at 8:38 PM Marc Zyngier wrote: > > > > On Wed, 20 Oct 2021 15:33:49 +0100, > > Anup Patel wrote: > > > > > > On Wed, Oct 20, 2021 at 7:04 PM Marc Zyngier wrote: > > > > > > > > On Tue, 19 Oct 2021 14:27:02 +0100, > > > > Guo Ren wrote: > > > > > > > > > > On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier wrote: > > > > > > > > > > > > On Tue, 19 Oct 2021 10:33:49 +0100, > > > > > > Guo Ren wrote: > > > > > > > > > > > > > > If you have an 'automask' behavior and yet the HW doesn't record this > > > > > > > > in a separate bit, then you need to track this by yourself in the > > > > > > > > irq_eoi() callback instead. I guess that you would skip the write to > > > > > > > > the CLAIM register in this case, though I have no idea whether this > > > > > > > > breaks > > > > > > > > the HW interrupt state or not. > > > > > > > The problem is when enable bit is 0 for that irq_number, > > > > > > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > > > > > > > the hw state machine. Then this irq would enter in ack state and no > > > > > > > continues irqs could come in. > > > > > > > > > > > > Really? This means that you cannot mask an interrupt while it is being > > > > > > handled? How great... > > > > > If the completion ID does not match an interrupt source that is > > > > > currently enabled for the target, the completion is silently ignored. > > > > > So, C9xx completion depends on enable-bit. > > > > > > > > Is that what the PLIC spec says? Or what your implementation does? I > > > > can understand that one implementation would be broken, but if the > > > > PLIC architecture itself is broken, that's far more concerning. > > > > > > Yes, we are dealing with a broken/non-compliant PLIC > > > implementation. > > > > > > The RISC-V PLIC spec defines a very different behaviour for the > > > interrupt claim (i.e. readl(claim)) and interrupt completion (i.e. > > > writel(claim)). The T-HEAD PLIC implementation does things > > > different from what the RISC-V PLIC spec says because it will > > > mask an interrupt upon interrupt claim whereas PLIC spec says > > > it should only clear the interrupt pending bit (not mask the interrupt). > > > > > > Quoting interrupt claim process (chapter 9) from PLIC spec: > > > "The PLIC can perform an interrupt claim by reading the claim/complete > > > register, which returns the ID of the highest priority pending interrupt or > > > zero if there is no pending interrupt. A successful claim will also atomically > > > clear the corresponding pending bit on the interrupt source." > > > > > > Refer, https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc > > > > That's not the point I'm making. According to Guo, the PLIC (any > > implementation of it) will ignore a write to claim on a masked > > interrupt. > > Yes, write to claim on a masked interrupt is certainly ignored but > read to claim does not automatically mask the interrupt. > > > > > If that's indeed correct, then a sequence such as: > > > > (1) irq = read(claim) > > This will return highest priority pending interrupt and clear the > pending bit as-per RISC-V PLIC spec. > > > (2) mask from the interrupt handler with the right flags so that it > > isn't done lazily > > (3) write(irq, claim) > > > > will result in an interrupt blocked in ack state (and probably no more > > interrupt for this CPU at this priority). That would be an interesting > > bug in the current code, but also a pretty bad architectural choice. > > The interrupt claim/completion is for each interrupt and not at CPU > level so if an interrupt is masked then only that interrupt is blocked > for all CPUs but other interrupts can still be raised. Do you mean that another interrupt of the same priority will be able to be taken on *this* CPU, despite the completion being silently ignored? M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28943C433EF for ; Wed, 20 Oct 2021 16:48:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D863C61374 for ; Wed, 20 Oct 2021 16:48:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D863C61374 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 20 Oct 2021 16:48:41 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mdElb-000U2P-6W; Wed, 20 Oct 2021 17:48:39 +0100 Date: Wed, 20 Oct 2021 17:48:38 +0100 Message-ID: <87y26nbq1l.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Guo Ren , Samuel Holland , Atish Patra , Thomas Gleixner , Palmer Dabbelt , Heiko =?UTF-8?B?U3TDvGJuZXI=?= , Rob Herring , Linux Kernel Mailing List , linux-riscv , Guo Ren Subject: Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support In-Reply-To: References: <20211016032200.2869998-1-guoren@kernel.org> <20211016032200.2869998-2-guoren@kernel.org> <8be1bdbd-365d-cd28-79d7-b924908f9e39@sholland.org> <8735oxuxlq.wl-maz@kernel.org> <875ytrddma.wl-maz@kernel.org> <871r4fd996.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anup@brainfault.org, guoren@kernel.org, samuel@sholland.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_094841_943215_FF4924FF X-CRM114-Status: GOOD ( 43.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, 20 Oct 2021 17:08:36 +0100, Anup Patel wrote: > > On Wed, Oct 20, 2021 at 8:38 PM Marc Zyngier wrote: > > > > On Wed, 20 Oct 2021 15:33:49 +0100, > > Anup Patel wrote: > > > > > > On Wed, Oct 20, 2021 at 7:04 PM Marc Zyngier wrote: > > > > > > > > On Tue, 19 Oct 2021 14:27:02 +0100, > > > > Guo Ren wrote: > > > > > > > > > > On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier wrote: > > > > > > > > > > > > On Tue, 19 Oct 2021 10:33:49 +0100, > > > > > > Guo Ren wrote: > > > > > > > > > > > > > > If you have an 'automask' behavior and yet the HW doesn't record this > > > > > > > > in a separate bit, then you need to track this by yourself in the > > > > > > > > irq_eoi() callback instead. I guess that you would skip the write to > > > > > > > > the CLAIM register in this case, though I have no idea whether this > > > > > > > > breaks > > > > > > > > the HW interrupt state or not. > > > > > > > The problem is when enable bit is 0 for that irq_number, > > > > > > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > > > > > > > the hw state machine. Then this irq would enter in ack state and no > > > > > > > continues irqs could come in. > > > > > > > > > > > > Really? This means that you cannot mask an interrupt while it is being > > > > > > handled? How great... > > > > > If the completion ID does not match an interrupt source that is > > > > > currently enabled for the target, the completion is silently ignored. > > > > > So, C9xx completion depends on enable-bit. > > > > > > > > Is that what the PLIC spec says? Or what your implementation does? I > > > > can understand that one implementation would be broken, but if the > > > > PLIC architecture itself is broken, that's far more concerning. > > > > > > Yes, we are dealing with a broken/non-compliant PLIC > > > implementation. > > > > > > The RISC-V PLIC spec defines a very different behaviour for the > > > interrupt claim (i.e. readl(claim)) and interrupt completion (i.e. > > > writel(claim)). The T-HEAD PLIC implementation does things > > > different from what the RISC-V PLIC spec says because it will > > > mask an interrupt upon interrupt claim whereas PLIC spec says > > > it should only clear the interrupt pending bit (not mask the interrupt). > > > > > > Quoting interrupt claim process (chapter 9) from PLIC spec: > > > "The PLIC can perform an interrupt claim by reading the claim/complete > > > register, which returns the ID of the highest priority pending interrupt or > > > zero if there is no pending interrupt. A successful claim will also atomically > > > clear the corresponding pending bit on the interrupt source." > > > > > > Refer, https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc > > > > That's not the point I'm making. According to Guo, the PLIC (any > > implementation of it) will ignore a write to claim on a masked > > interrupt. > > Yes, write to claim on a masked interrupt is certainly ignored but > read to claim does not automatically mask the interrupt. > > > > > If that's indeed correct, then a sequence such as: > > > > (1) irq = read(claim) > > This will return highest priority pending interrupt and clear the > pending bit as-per RISC-V PLIC spec. > > > (2) mask from the interrupt handler with the right flags so that it > > isn't done lazily > > (3) write(irq, claim) > > > > will result in an interrupt blocked in ack state (and probably no more > > interrupt for this CPU at this priority). That would be an interesting > > bug in the current code, but also a pretty bad architectural choice. > > The interrupt claim/completion is for each interrupt and not at CPU > level so if an interrupt is masked then only that interrupt is blocked > for all CPUs but other interrupts can still be raised. Do you mean that another interrupt of the same priority will be able to be taken on *this* CPU, despite the completion being silently ignored? M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv