From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00A68C433EF for ; Thu, 23 Sep 2021 14:36:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF818611C6 for ; Thu, 23 Sep 2021 14:36:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241688AbhIWOiZ (ORCPT ); Thu, 23 Sep 2021 10:38:25 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:34926 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241565AbhIWOiX (ORCPT ); Thu, 23 Sep 2021 10:38:23 -0400 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1632407811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=qk5SWtvWztav1d34rimp+axwz2uAlkSCirHPCi6SGlY=; b=g7Ek/TeFULsF7sK6OQfwNWOX61vf8REKAJRK7IzhTXeBgOdV/Diko4a0P5+bQYnb07elR0 s4ILsOk9KJsvfxL22o7/g/MPCbxlEvFa+0QeN91yGuF2dmYeNYy/k9vC84EJ3Hoajn2v1K WcIiM/nIav37yMi6oFosTp93wFq+qzFfi9tdwoG8pSEvXFOO1X/YqGOdx8LPLEujT54F4o q6zuR8YcaHraOlkIYkj8tThSId7POAlsuQKadr1x777hR72nYITCYMG88C0BOJO3ug0Tqe sx8fGggxr6c3LRp2oSd86MaIK+H9fpdZZbmCCoQF9W1A7ELAXs+fs/abt7khnA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1632407811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=qk5SWtvWztav1d34rimp+axwz2uAlkSCirHPCi6SGlY=; b=H6dvkkN47bCyZzwlY0JUFQ7uATY2ql1mGO4cHSy6395KBmgE8LpdjVgsY+g0mML0arQgcv ryxelQSmTKi+KUCQ== To: Fenghua Yu , Ingo Molnar , Borislav Petkov , Peter Zijlstra , Andy Lutomirski , Dave Hansen , Tony Luck , Lu Baolu , Joerg Roedel , Josh Poimboeuf , Dave Jiang , Jacob Jun Pan , Ashok Raj , Ravi V Shankar Cc: iommu@lists.linux-foundation.org, x86 , linux-kernel , Fenghua Yu Subject: Re: [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting In-Reply-To: <20210920192349.2602141-6-fenghua.yu@intel.com> References: <20210920192349.2602141-1-fenghua.yu@intel.com> <20210920192349.2602141-6-fenghua.yu@intel.com> Date: Thu, 23 Sep 2021 16:36:50 +0200 Message-ID: <87y27nfjel.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 20 2021 at 19:23, Fenghua Yu wrote: > > +#ifdef CONFIG_INTEL_IOMMU_SVM > +void pasid_put(struct task_struct *tsk, struct mm_struct *mm); > +#else > +static inline void pasid_put(struct task_struct *tsk, struct mm_struct *mm) { } > +#endif This code is again defining that PASID is entirely restricted to INTEL. It's true, that no other vendor supports this, but PASID is a non-vendor specific concept. Sticking this into INTEL code means that any other PASID implementation has to rip it out again from INTEL code and make it a run time property. The refcounting issue should be the same for all PASID mechanisms which attach PASID to a mm. What's INTEL specific about that? So can we pretty please do that correct right away? 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1632407811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=qk5SWtvWztav1d34rimp+axwz2uAlkSCirHPCi6SGlY=; b=H6dvkkN47bCyZzwlY0JUFQ7uATY2ql1mGO4cHSy6395KBmgE8LpdjVgsY+g0mML0arQgcv ryxelQSmTKi+KUCQ== To: Fenghua Yu , Ingo Molnar , Borislav Petkov , Peter Zijlstra , Andy Lutomirski , Dave Hansen , Tony Luck , Lu Baolu , Joerg Roedel , Josh Poimboeuf , Dave Jiang , Jacob Jun Pan , Ashok Raj , Ravi V Shankar Subject: Re: [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting In-Reply-To: <20210920192349.2602141-6-fenghua.yu@intel.com> References: <20210920192349.2602141-1-fenghua.yu@intel.com> <20210920192349.2602141-6-fenghua.yu@intel.com> Date: Thu, 23 Sep 2021 16:36:50 +0200 Message-ID: <87y27nfjel.ffs@tglx> MIME-Version: 1.0 Cc: Fenghua Yu , iommu@lists.linux-foundation.org, x86 , linux-kernel X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, Sep 20 2021 at 19:23, Fenghua Yu wrote: > > +#ifdef CONFIG_INTEL_IOMMU_SVM > +void pasid_put(struct task_struct *tsk, struct mm_struct *mm); > +#else > +static inline void pasid_put(struct task_struct *tsk, struct mm_struct *mm) { } > +#endif This code is again defining that PASID is entirely restricted to INTEL. It's true, that no other vendor supports this, but PASID is a non-vendor specific concept. Sticking this into INTEL code means that any other PASID implementation has to rip it out again from INTEL code and make it a run time property. The refcounting issue should be the same for all PASID mechanisms which attach PASID to a mm. What's INTEL specific about that? So can we pretty please do that correct right away? Thanks, tglx _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu