From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 351CBC4320A for ; Thu, 5 Aug 2021 07:39:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 147FE60F94 for ; Thu, 5 Aug 2021 07:39:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232323AbhHEHjg (ORCPT ); Thu, 5 Aug 2021 03:39:36 -0400 Received: from mail.kernel.org ([198.145.29.99]:58024 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230471AbhHEHjg (ORCPT ); Thu, 5 Aug 2021 03:39:36 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9467860F10; Thu, 5 Aug 2021 07:39:22 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mBXyK-0034vy-Iv; Thu, 05 Aug 2021 08:39:20 +0100 Date: Thu, 05 Aug 2021 08:39:20 +0100 Message-ID: <87y29gbas7.wl-maz@kernel.org> From: Marc Zyngier To: Sam Protsenko Cc: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support In-Reply-To: References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-13-semen.protsenko@linaro.org> <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> <87k0l1w8y5.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: semen.protsenko@linaro.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, krzysztof.kozlowski@canonical.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, jirislaby@kernel.org, gregkh@linuxfoundation.org, ckeepax@opensource.wolfsonmicro.com, ryu.real@samsung.com, tom.gall@linaro.org, sumit.semwal@linaro.org, john.stultz@linaro.org, amit.pundir@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Wed, 04 Aug 2021 19:37:24 +0100, Sam Protsenko wrote: > > On Wed, 4 Aug 2021 at 18:01, Marc Zyngier wrote: > > > > On Wed, 04 Aug 2021 15:39:38 +0100, > > Sam Protsenko wrote: > > > > > > You are also missing the hypervisor virtual timer interrupt. > > > > > > > > > > Checked SoC TRM, there is no PPI for hypervisor virtual timer > > > interrupt, and no mentioning of it at all. Likewise, I checked ARMv8 > > > ARM and TRM, almost no description of it. Also, I checked other > > > platforms, and seems like everyone does the same (having only 4 > > > interrupts). And I wasn't able to find any documentation on that, so I > > > guess I'll leave it as is, if you don't mind. > > > > I *do* mind, and other DTs being wrong isn't a good enough excuse! ;-) > > > > From the ARMv8 ARM (ARM DDI 0487G.b) > > > > D11.2.4 Timers > > > > In an implementation of the Generic Timer that includes EL3, if EL3 > > can use AArch64, the following timers are implemented: > > > > * An EL1 physical timer, that: > > - In Secure state, can be accessed from EL1. > > - In Non-secure state, can be accessed from EL1 unless those > > accesses are trapped to EL2. > > When this timer can be accessed from EL1, an EL1 control > > determines whether it can be accessed from EL0. > > * A Non-secure EL2 physical timer. > > * A Secure EL3 physical timer. An EL3 control determines whether this > > register is accessible from Secure EL1. > > * An EL1 virtual timer. > > * When FEAT_VHE is implemented, a Non-secure EL2 virtual timer. > > * When FEAT_SEL2 is implemented, a Secure EL2 physical timer. > > * When FEAT_SEL2 is implemented, a Secure EL2 virtual timer. > > > > > > Cortex-A55 being an ARMv8.2 implementation, it has FEAT_VHE, and thus > > it does have a NS-EL2 virtual timer. This is further confirmed by the > > TRM which documents CNTHV*_EL2 as valid system registers[1]. > > > > So the timer exists, the signal is routed out of the core, and it > > is likely that it is connected to the GIC. > > > > If the designers have omitted it, then it needs to be documented as > > such. > > > > Ok, I've checked thoroughly all docs again, and it seems like there is > no dedicated PPI number for this "EL2 Hypervisor Virtual Timer" in > Exynos850 SoC. The timer instance itself might exist of course, but > interrupt line is probably wasn't connected to GIC by SoC designers, > at least it's not documented. Can you try and check this? You can directly program the virtual timer so that it has a pending interrupt, and then check the pending register on the same CPU to see if there is anything appearing there. > Moreover, from [1,2] it looks like if it were existing it would have > been PPI=12 (INTID=28). But in GIC-400 TRM this PPI is assigned to > "Legacy FIQ signal", No. That's only if you set the bypass bits in GICD_CTLR, which nobody with half a brain would consider doing. > and all there is no PPI for Hypervisor Virtual > Timer documented there as well. In Exynos850 TRM the source for this > PPI's interrupt source is marked as "-", which means it's not used. > > So if you know something that I don't know -- please point me out the > doc where this PPI line is documented. Otherwise I can add the comment > to device tree, stating that this interrupt line is not present in > SoC's GIC, i.e. something like this: > > 8<------------------------------------------------------------------------------->8 > timer { > compatible = "arm,armv8-timer"; > interrupts = IRQ_TYPE_LEVEL_LOW)>, > IRQ_TYPE_LEVEL_LOW)>, > IRQ_TYPE_LEVEL_LOW)>, > IRQ_TYPE_LEVEL_LOW)>; > /* Hypervisor Virtual Timer PPI is not present in this SoC GIC */ > }; > 8<------------------------------------------------------------------------------->8 > > Is that ok with you? I'd rather you verify the above first. And if you can't, I'd like a comment that is a bit more explicit: /* The vendor couldn't be bothered to wire the EL2 Virtual Timers */ Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1B52C4338F for ; Thu, 5 Aug 2021 07:40:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 80E0D60F10 for ; Thu, 5 Aug 2021 07:40:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 80E0D60F10 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; 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Thu, 05 Aug 2021 07:39:27 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mBXyN-008QX5-1r for linux-arm-kernel@lists.infradead.org; Thu, 05 Aug 2021 07:39:24 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9467860F10; Thu, 5 Aug 2021 07:39:22 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mBXyK-0034vy-Iv; Thu, 05 Aug 2021 08:39:20 +0100 Date: Thu, 05 Aug 2021 08:39:20 +0100 Message-ID: <87y29gbas7.wl-maz@kernel.org> From: Marc Zyngier To: Sam Protsenko Cc: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support In-Reply-To: References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-13-semen.protsenko@linaro.org> <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> <87k0l1w8y5.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: semen.protsenko@linaro.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, krzysztof.kozlowski@canonical.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, jirislaby@kernel.org, gregkh@linuxfoundation.org, ckeepax@opensource.wolfsonmicro.com, ryu.real@samsung.com, tom.gall@linaro.org, sumit.semwal@linaro.org, john.stultz@linaro.org, amit.pundir@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210805_003923_198286_A6541DDA X-CRM114-Status: GOOD ( 47.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 04 Aug 2021 19:37:24 +0100, Sam Protsenko wrote: > > On Wed, 4 Aug 2021 at 18:01, Marc Zyngier wrote: > > > > On Wed, 04 Aug 2021 15:39:38 +0100, > > Sam Protsenko wrote: > > > > > > You are also missing the hypervisor virtual timer interrupt. > > > > > > > > > > Checked SoC TRM, there is no PPI for hypervisor virtual timer > > > interrupt, and no mentioning of it at all. Likewise, I checked ARMv8 > > > ARM and TRM, almost no description of it. Also, I checked other > > > platforms, and seems like everyone does the same (having only 4 > > > interrupts). And I wasn't able to find any documentation on that, so I > > > guess I'll leave it as is, if you don't mind. > > > > I *do* mind, and other DTs being wrong isn't a good enough excuse! ;-) > > > > From the ARMv8 ARM (ARM DDI 0487G.b) > > > > D11.2.4 Timers > > > > In an implementation of the Generic Timer that includes EL3, if EL3 > > can use AArch64, the following timers are implemented: > > > > * An EL1 physical timer, that: > > - In Secure state, can be accessed from EL1. > > - In Non-secure state, can be accessed from EL1 unless those > > accesses are trapped to EL2. > > When this timer can be accessed from EL1, an EL1 control > > determines whether it can be accessed from EL0. > > * A Non-secure EL2 physical timer. > > * A Secure EL3 physical timer. An EL3 control determines whether this > > register is accessible from Secure EL1. > > * An EL1 virtual timer. > > * When FEAT_VHE is implemented, a Non-secure EL2 virtual timer. > > * When FEAT_SEL2 is implemented, a Secure EL2 physical timer. > > * When FEAT_SEL2 is implemented, a Secure EL2 virtual timer. > > > > > > Cortex-A55 being an ARMv8.2 implementation, it has FEAT_VHE, and thus > > it does have a NS-EL2 virtual timer. This is further confirmed by the > > TRM which documents CNTHV*_EL2 as valid system registers[1]. > > > > So the timer exists, the signal is routed out of the core, and it > > is likely that it is connected to the GIC. > > > > If the designers have omitted it, then it needs to be documented as > > such. > > > > Ok, I've checked thoroughly all docs again, and it seems like there is > no dedicated PPI number for this "EL2 Hypervisor Virtual Timer" in > Exynos850 SoC. The timer instance itself might exist of course, but > interrupt line is probably wasn't connected to GIC by SoC designers, > at least it's not documented. Can you try and check this? You can directly program the virtual timer so that it has a pending interrupt, and then check the pending register on the same CPU to see if there is anything appearing there. > Moreover, from [1,2] it looks like if it were existing it would have > been PPI=12 (INTID=28). But in GIC-400 TRM this PPI is assigned to > "Legacy FIQ signal", No. That's only if you set the bypass bits in GICD_CTLR, which nobody with half a brain would consider doing. > and all there is no PPI for Hypervisor Virtual > Timer documented there as well. In Exynos850 TRM the source for this > PPI's interrupt source is marked as "-", which means it's not used. > > So if you know something that I don't know -- please point me out the > doc where this PPI line is documented. Otherwise I can add the comment > to device tree, stating that this interrupt line is not present in > SoC's GIC, i.e. something like this: > > 8<------------------------------------------------------------------------------->8 > timer { > compatible = "arm,armv8-timer"; > interrupts = IRQ_TYPE_LEVEL_LOW)>, > IRQ_TYPE_LEVEL_LOW)>, > IRQ_TYPE_LEVEL_LOW)>, > IRQ_TYPE_LEVEL_LOW)>; > /* Hypervisor Virtual Timer PPI is not present in this SoC GIC */ > }; > 8<------------------------------------------------------------------------------->8 > > Is that ok with you? I'd rather you verify the above first. And if you can't, I'd like a comment that is a bit more explicit: /* The vendor couldn't be bothered to wire the EL2 Virtual Timers */ Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel