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X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "thuth@redhat.com" , "dovgaluk@ispras.ru" , "richard.henderson@linaro.org" , Michael Rolnik , "imammedo@redhat.com" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Aleksandar Markovic writes: > On Friday, October 11, 2019, Philippe Mathieu-Daud=C3=A9 > wrote: > >> Hi Michael, >> >> On 9/2/19 4:01 PM, Michael Rolnik wrote: >> >>> This series of patches adds 8bit AVR cores to QEMU. >>> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully >>> tested yet. >>> However I was able to execute simple code with functions. e.g fibonacci >>> calculation. >>> This series of patches include a non real, sample board. >>> No fuses support yet. PC is set to 0 at reset. >>> >>> the patches include the following >>> 1. just a basic 8bit AVR CPU, without instruction decoding or translati= on >>> 2. CPU features which allow define the following 8bit AVR cores >>> avr1 >>> avr2 avr25 >>> avr3 avr31 avr35 >>> avr4 >>> avr5 avr51 >>> avr6 >>> xmega2 xmega4 xmega5 xmega6 xmega7 >>> 3. a definition of sample machine with SRAM, FLASH and CPU which allows >>> to execute simple code >>> 4. encoding for all AVR instructions >>> 5. interrupt handling >>> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions >>> 7. a decoder which given an opcode decides what istruction it is >>> 8. translation of AVR instruction into TCG >>> 9. all features together >>> >>> [..] >> >>> Michael Rolnik (7): >>> target/avr: Add outward facing interfaces and core CPU logic >>> target/avr: Add instruction helpers >>> target/avr: Add instruction decoding >>> target/avr: Add instruction translation >>> target/avr: Add example board configuration >>> target/avr: Register AVR support with the rest of QEMU, the build >>> system, and the MAINTAINERS file >>> target/avr: Add tests >>> >>> Sarah Harris (1): >>> target/avr: Add limited support for USART and 16 bit timer periphera= ls >>> >> >> Overall architecture patches look good, but I'd like some more time to >> review the hardware patches. Unfortunately I won't have time until Novem= ber. >> There was a chat on IRC about your series, >> > I don't see the reason why do you initiate IRC communication on this topi= c, > if we have the mailing list for discussing such important issues as > introducing a new target (that should be definitely visible to all > participants). IRC is often a good way of quickly discussing something when someone is about (often as a tangent from another discussion). I don't think there is anything wrong with that as long as it's followed up on the mailing list. > >> I suggested Richard we could merge patches 1-4 and 7. They are almost >> sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS >> ones). Which is was ;-) -- Alex Benn=C3=A9e