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X-Received-From: 2a00:1450:4864:20::341 Subject: Re: [Qemu-devel] [PATCH v3 01/50] trace: expand mem_info:size_shift to 3 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Emilio G. Cota" , qemu-devel@nongnu.org, Stefan Hajnoczi Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > On 6/14/19 10:11 AM, Alex Benn=C3=A9e wrote: >> From: "Emilio G. Cota" >> >> This will allow us to trace 16B-long memory accesses. >> >> Reviewed-by: Alex Benn=C3=A9e >> Signed-off-by: Emilio G. Cota >> --- >> trace-events | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/trace-events b/trace-events >> index 844ee58dd9..037169aab3 100644 >> --- a/trace-events >> +++ b/trace-events >> @@ -159,7 +159,7 @@ vcpu guest_cpu_reset(void) >> # Access information can be parsed as: >> # >> # struct mem_info { >> -# uint8_t size_shift : 2; /* interpreted as "1 << size_shift" bytes= */ >> +# uint8_t size_shift : 3; /* interpreted as "1 << size_shift" bytes= */ >> # bool sign_extend: 1; /* sign-extended */ >> # uint8_t endianness : 1; /* 0: little, 1: big */ >> # bool store : 1; /* wheter it's a store operation */ >> > > Well, 128B-long memory accesses. But SVE supports 256B memory accesses > already. So why not add one more bit now. Good point. Do we have any architectures that do load/stores that are not power of 2? I guess the SVE non-faulting accesses are treated as a series of elem size accesses. > > > r~ -- Alex Benn=C3=A9e