From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com ([192.55.52.43]:25408 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932231AbcJZTIs (ORCPT ); Wed, 26 Oct 2016 15:08:48 -0400 From: Jani Nikula To: "Pandiyan\, Dhinakaran" Cc: "ville.syrjala\@linux.intel.com" , "intel-gfx\@lists.freedesktop.org" , "stable\@vger.kernel.org" Subject: Re: [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio In-Reply-To: <1477507068.3808.16.camel@dk-H97M-D3H> References: <87d1iooknr.fsf@intel.com> <1477438863-20299-1-git-send-email-dhinakaran.pandiyan@intel.com> <874m3zmqx9.fsf@intel.com> <1477507068.3808.16.camel@dk-H97M-D3H> Date: Wed, 26 Oct 2016 22:08:44 +0300 Message-ID: <87y41blygz.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org List-ID: On Wed, 26 Oct 2016, "Pandiyan, Dhinakaran" wrote: > On Wed, 2016-10-26 at 11:54 +0300, Jani Nikula wrote: >> On Wed, 26 Oct 2016, Dhinakaran Pandiyan wrote: >> > According to BSpec, cdclk has to be not less than 432 MHz with DP audio >> > enabled, port width x4, and link rate HBR2 (5.4 GHz) >> > >> > Having a lower cdclk triggers pipe underruns, which then lead to displays >> > continuously cycling off and on. This is essential for DP MST audio as the >> > link is trained at HBR2 and 4 lanes by default. >> > >> > v3: Combine BDW pixel rate adjustments into a function (Jani) >> > v2: Restrict fix to BDW >> > Retain the set cdclk across modesets (Ville) >> > Cc: stable@vger.kernel.org >> > Signed-off-by: Dhinakaran Pandiyan >> > Reviewed-by: Ville Syrjälä >> >> Reviewed-by: Jani Nikula >> >> We'll need this fix for Skylake too, don't we? Maybe Kabylake? Please >> send a follow-up patch for Skylake with the changes mentioned inline >> below. >> >> BR, >> Jani. >> >> > > Patch 1/2 should take care of gen9 platforms when audio sampling rates > are <= 96 kHz. I am still not sure how to increase increase cdclk when > the sampling rates > 96kHZ , that is why I have added the TODO in Patch > 1/2. IIUC the two patches and fixes are related, but separate. This one requires 4 lanes, the other one doesn't. For this one there's no mention of audio sampling rate. BR, Jani. > >> > --- >> > drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- >> > 1 file changed, 24 insertions(+), 3 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> > index a94f7d1..efe46b4 100644 >> > --- a/drivers/gpu/drm/i915/intel_display.c >> > +++ b/drivers/gpu/drm/i915/intel_display.c >> > @@ -10260,6 +10260,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) >> > bxt_set_cdclk(to_i915(dev), req_cdclk); >> > } >> > >> > +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, >> > + int pixel_rate) >> > +{ >> > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ >> > + if (crtc_state->ips_enabled) >> >> if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) >> >> > + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); >> > + >> > + /* BSpec says "Do not use DisplayPort with CDCLK less than >> > + * 432 MHz, audio enabled, port width x4, and link rate >> > + * HBR2 (5.4 GHz), or else there may be audio corruption or >> > + * screen corruption." >> > + */ >> > + if (intel_crtc_has_dp_encoder(crtc_state) && >> > + crtc_state->has_audio && >> > + crtc_state->port_clock >= 540000 && >> > + crtc_state->lane_count == 4) >> > + pixel_rate = max(432000, pixel_rate); >> > + >> > + return pixel_rate; >> > +} >> > + >> > /* compute the max rate for new configuration */ >> > static int ilk_max_pixel_rate(struct drm_atomic_state *state) >> > { >> > @@ -10285,9 +10306,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) >> > >> > pixel_rate = ilk_pipe_pixel_rate(crtc_state); >> > >> > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ >> > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) >> > - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); >> > + if (IS_BROADWELL(dev_priv)) >> >> if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) >> >> > + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, >> > + pixel_rate); >> > >> > intel_state->min_pixclk[i] = pixel_rate; >> > } >> > -- Jani Nikula, Intel Open Source Technology Center From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio Date: Wed, 26 Oct 2016 22:08:44 +0300 Message-ID: <87y41blygz.fsf@intel.com> References: <87d1iooknr.fsf@intel.com> <1477438863-20299-1-git-send-email-dhinakaran.pandiyan@intel.com> <874m3zmqx9.fsf@intel.com> <1477507068.3808.16.camel@dk-H97M-D3H> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E7556E0EE for ; Wed, 26 Oct 2016 19:08:53 +0000 (UTC) In-Reply-To: <1477507068.3808.16.camel@dk-H97M-D3H> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Pandiyan, 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