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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Nada Lachtar <nlachtar@umich.edu>
Cc: qemu-devel@nongnu.org, Richard Henderson <richard.henderson@linaro.org>
Subject: Re: Question about TLBs
Date: Sat, 31 Dec 2022 20:04:08 +0000	[thread overview]
Message-ID: <87zgb3qqrm.fsf@linaro.org> (raw)
In-Reply-To: <C2E99F08-5683-4332-B4F6-E3BACFAB6423@umich.edu>


Nada Lachtar <nlachtar@umich.edu> writes:

> [[S/MIME Signed Part:Undecided]]
> Hello,
>
> Does Qemu maintain two TLB for the x86_64 system (i.e iTLB and dTLB)?
> If yes, can you please point me to how to access the dTLB and what
> data structure maintains this information!

Qemu's internal softmmu TLB is unified and holds information for code
loads, memory accesses and re-directions for io access. See CPUTLBEntry
and CPUTLBEntryFull. They do not directly map onto any target specific
structures (although targets can use TARGET_PAGE_ENTRY_EXTRA to store
extra information in the table).

These entries are filled by target specific code via
cpu->cc->tcg_ops->tlb_fill() which in the x86 case takes you to
x86_cpu_tlb_fill(). This is the code responsible to walking the target
page tables and filling in the details of the mappings.

>
> I would appreciate any help,
>
>
> Thanks,
>
>
>
>
> [[End of S/MIME Signed Part]]


-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro


      reply	other threads:[~2022-12-31 20:10 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-31  9:39 Question about TLBs Nada Lachtar
2022-12-31 20:04 ` Alex Bennée [this message]

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