From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AEA7CCA479 for ; Sat, 25 Jun 2022 16:06:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233258AbiFYQGC (ORCPT ); Sat, 25 Jun 2022 12:06:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233242AbiFYQGA (ORCPT ); Sat, 25 Jun 2022 12:06:00 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DB4B167F3; Sat, 25 Jun 2022 09:05:59 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id B6851B80C2C; Sat, 25 Jun 2022 16:05:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61259C3411C; Sat, 25 Jun 2022 16:05:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656173156; bh=AToRdKG3QacktWi9IxW2BHWjWYtnPEVe84zJg54fJbA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=fGwapFIFYQVzdVIiYmnOpMXFdnjqbX7gyB8aL6hlrOh+99RVXILoAKibc4r6AmJk1 W2V/iC/ytjfLhCPXtoWAx1T5i0Zn3cUBWsYueq3MBFUjMcR2MehYpSd4JbEEbmRQAv CQfhbX+NjKUTM7Bt79ck+4gj7H+MqrA5tCXwsOCPIrFHH9UXPyai2VXbX9z37KVEHU UeH5qkHiFsPbV+nB7K0zFgRf7vI+eW1Vk+sV6vQG6VTSBMDWkotVqPuMrWUC1EKmvj vLpfa6vmV3g/P2zkaLdqHTF0wfnar0Oo0+lh+yKeru11eGZGDeW0lcF0f0jeEWQl3v F4lw0It6clzXw== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o58IE-0035Px-7I; Sat, 25 Jun 2022 17:05:54 +0100 Date: Sat, 25 Jun 2022 17:05:59 +0100 Message-ID: <87zgi0eniw.wl-maz@kernel.org> From: Marc Zyngier To: "Lad, Prabhakar" Cc: Lad Prabhakar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Geert Uytterhoeven , Linux-Renesas , LKML , Biju Das Subject: Re: [PATCH 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC In-Reply-To: References: <20220624180311.3007-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220624180311.3007-3-prabhakar.mahadev-lad.rj@bp.renesas.com> <8735ftf73p.wl-maz@kernel.org> <87h7492c58.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: prabhakar.csengg@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sagar.kadam@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, biju.das.jz@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 25 Jun 2022 14:03:33 +0100, "Lad, Prabhakar" wrote: > > [1 ] > Hi Marc, > > On Sat, Jun 25, 2022 at 12:52 PM Marc Zyngier wrote: > > [...] > > You are just reinventing the wheel we are already have, except that > > yours is a bit square ;-). What really should happen is that the > > set_type method should set the correct flow depending on the trigger > > of the interrupt, and *never* have to check the configuration on the > > handling path. > > > A Bit lost here.. > > We have the below chained handler: > > static void plic_handle_irq(struct irq_desc *desc) > { > struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > struct irq_chip *chip = irq_desc_get_chip(desc); > void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; > irq_hw_number_t hwirq; > > WARN_ON_ONCE(!handler->present); > > chained_irq_enter(chip, desc); > > while ((hwirq = readl(claim))) { > int err = generic_handle_domain_irq(handler->priv->irqdomain, > hwirq); > if (unlikely(err)) > pr_warn_ratelimited("can't find mapping for hwirq %lu\n", > hwirq); > } > > chained_irq_exit(chip, desc); > } > > static void plic_irq_eoi(struct irq_data *d) > { > struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > > if (irqd_irq_masked(d)) { > plic_irq_unmask(d); > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > plic_irq_mask(d); > } else { > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > } > } > > Where it's claiming -> handling interrupt -> interrupt completion in > eoi which is according to architecture. > > > Now with fasteoi_ack flow If I introduce the below ack callback to > issue interrupt completion. > > static void plic_irq_ack(struct irq_data *d) > { > struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > > if (irqd_irq_masked(d)) { > plic_irq_unmask(d); > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > plic_irq_mask(d); > } else { > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > } > } > > Here we are issuing an interrupt completion first, and later in the > handler plic_handle_irq() we are claiming the interrupt by reading > the claim register. With this we are not following [0]. Whatever [0] says doesn't really matter, since the HW is totally busted. > Do you think this flow is OK (interrupt completion -> Interrupt claim > -> handle IRQ)? You keep missing my point. Edge and Level *must* have different flows and this also implies different callbacks. You can't just handle both at once. You should have something like this (untested): diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index bb87e4c3b88e..5e072be32d9f 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -176,16 +176,52 @@ static void plic_irq_eoi(struct irq_data *d) } } +static int broken_set_type(struct irq_data *d, unsigned int type); + static struct irq_chip plic_chip = { .name = "SiFive PLIC", .irq_mask = plic_irq_mask, .irq_unmask = plic_irq_unmask, .irq_eoi = plic_irq_eoi, + .irq_set_type = broken_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = plic_set_affinity, +#endif +}; + +static void broken_eoi(struct irq_data *data) {} + +static struct irq_chip plic_chip_edge = { + .name = "Edgy PLIC", + .irq_mask = plic_irq_mask, + .irq_unmask = plic_irq_unmask, + .irq_ack = plic_irq_eoi, + .irq_eoi = broken_eoi, + .irq_set_type = broken_set_type, #ifdef CONFIG_SMP .irq_set_affinity = plic_set_affinity, #endif }; +static int broken_set_type(struct irq_data *d, unsigned int type) +{ + if (!plic_is_totaly_broken()) + return 0; + + if (type == IRQ_TYPE_EDGE_RISING) + irq_set_chip_handler_name_locked(d, plic_chip_edge, + handle_fasteoi_ack_irq, + "Edge"); + else if (type == IRQ_TYPE_LEVEL_HIGH) + irq_set_chip_handler_name_locked(d, plic_chip, + handle_fasteoi_irq, + "Level"); + else + return -EINVAL; + + return 0; +} + static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { which applies the correct flow and chip depending on the trigger information. This also implies that for chained PLICs, the secondary PLIC output is handled as a level into the primary PLIC. M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2795C433EF for ; Sat, 25 Jun 2022 16:06:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=n0Cv8g7GsqeGObMWxQvNKxzgw+cLzVB8M3ZFtXfP5eE=; b=DobQqn30dT5H0K Km/+wSNjCn4NwsMFdohx53XPYhAK1FlCiriuuWVPWVEBIn4iLWB78CPEAmf0HhGLbZ3ok20RtiguM 3GQbScxvxfdydhE7PCiV203JHTnNrFbj7DAJgapl2fd08HFvnzqapQZj6yZQeS+lDITEeAfRhwpwv NFeohGJOvha/UnHKt+G+ErjkJMrIql14IpqvtG46N/uLFjJ6Sb1/B0+Iq08b7/UZOE25wajPywVNx kzkBg7sWNyskUuA7TKC6rB8L1A6ZRe9SeNyRGksMwXfrsHCaCDhFm05uRGf6pke5xpA9omEF2avP4 BFB0LiM5ZVt5dhVjBa1A==; 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Sat, 25 Jun 2022 17:05:54 +0100 Date: Sat, 25 Jun 2022 17:05:59 +0100 Message-ID: <87zgi0eniw.wl-maz@kernel.org> From: Marc Zyngier To: "Lad, Prabhakar" Cc: Lad Prabhakar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Geert Uytterhoeven , Linux-Renesas , LKML , Biju Das Subject: Re: [PATCH 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC In-Reply-To: References: <20220624180311.3007-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220624180311.3007-3-prabhakar.mahadev-lad.rj@bp.renesas.com> <8735ftf73p.wl-maz@kernel.org> <87h7492c58.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: prabhakar.csengg@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sagar.kadam@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, biju.das.jz@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220625_090559_493358_B23AB0DD X-CRM114-Status: GOOD ( 33.91 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, 25 Jun 2022 14:03:33 +0100, "Lad, Prabhakar" wrote: > > [1 ] > Hi Marc, > > On Sat, Jun 25, 2022 at 12:52 PM Marc Zyngier wrote: > > [...] > > You are just reinventing the wheel we are already have, except that > > yours is a bit square ;-). What really should happen is that the > > set_type method should set the correct flow depending on the trigger > > of the interrupt, and *never* have to check the configuration on the > > handling path. > > > A Bit lost here.. > > We have the below chained handler: > > static void plic_handle_irq(struct irq_desc *desc) > { > struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > struct irq_chip *chip = irq_desc_get_chip(desc); > void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; > irq_hw_number_t hwirq; > > WARN_ON_ONCE(!handler->present); > > chained_irq_enter(chip, desc); > > while ((hwirq = readl(claim))) { > int err = generic_handle_domain_irq(handler->priv->irqdomain, > hwirq); > if (unlikely(err)) > pr_warn_ratelimited("can't find mapping for hwirq %lu\n", > hwirq); > } > > chained_irq_exit(chip, desc); > } > > static void plic_irq_eoi(struct irq_data *d) > { > struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > > if (irqd_irq_masked(d)) { > plic_irq_unmask(d); > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > plic_irq_mask(d); > } else { > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > } > } > > Where it's claiming -> handling interrupt -> interrupt completion in > eoi which is according to architecture. > > > Now with fasteoi_ack flow If I introduce the below ack callback to > issue interrupt completion. > > static void plic_irq_ack(struct irq_data *d) > { > struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > > if (irqd_irq_masked(d)) { > plic_irq_unmask(d); > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > plic_irq_mask(d); > } else { > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > } > } > > Here we are issuing an interrupt completion first, and later in the > handler plic_handle_irq() we are claiming the interrupt by reading > the claim register. With this we are not following [0]. Whatever [0] says doesn't really matter, since the HW is totally busted. > Do you think this flow is OK (interrupt completion -> Interrupt claim > -> handle IRQ)? You keep missing my point. Edge and Level *must* have different flows and this also implies different callbacks. You can't just handle both at once. You should have something like this (untested): diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index bb87e4c3b88e..5e072be32d9f 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -176,16 +176,52 @@ static void plic_irq_eoi(struct irq_data *d) } } +static int broken_set_type(struct irq_data *d, unsigned int type); + static struct irq_chip plic_chip = { .name = "SiFive PLIC", .irq_mask = plic_irq_mask, .irq_unmask = plic_irq_unmask, .irq_eoi = plic_irq_eoi, + .irq_set_type = broken_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = plic_set_affinity, +#endif +}; + +static void broken_eoi(struct irq_data *data) {} + +static struct irq_chip plic_chip_edge = { + .name = "Edgy PLIC", + .irq_mask = plic_irq_mask, + .irq_unmask = plic_irq_unmask, + .irq_ack = plic_irq_eoi, + .irq_eoi = broken_eoi, + .irq_set_type = broken_set_type, #ifdef CONFIG_SMP .irq_set_affinity = plic_set_affinity, #endif }; +static int broken_set_type(struct irq_data *d, unsigned int type) +{ + if (!plic_is_totaly_broken()) + return 0; + + if (type == IRQ_TYPE_EDGE_RISING) + irq_set_chip_handler_name_locked(d, plic_chip_edge, + handle_fasteoi_ack_irq, + "Edge"); + else if (type == IRQ_TYPE_LEVEL_HIGH) + irq_set_chip_handler_name_locked(d, plic_chip, + handle_fasteoi_irq, + "Level"); + else + return -EINVAL; + + return 0; +} + static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { which applies the correct flow and chip depending on the trigger information. This also implies that for chained PLICs, the secondary PLIC output is handled as a level into the primary PLIC. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv