From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87519C43461 for ; Thu, 20 May 2021 12:59:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 64A6F6101D for ; Thu, 20 May 2021 12:59:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243453AbhETNBA (ORCPT ); Thu, 20 May 2021 09:01:00 -0400 Received: from mail.kernel.org ([198.145.29.99]:34430 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243276AbhETNAU (ORCPT ); Thu, 20 May 2021 09:00:20 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7DDC261004; Thu, 20 May 2021 12:58:58 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ljiGO-002aDT-6Q; Thu, 20 May 2021 13:58:56 +0100 Date: Thu, 20 May 2021 13:58:55 +0100 Message-ID: <87zgwptvcg.wl-maz@kernel.org> From: Marc Zyngier To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kernel-team@android.com, stable@vger.kernel.org, Steven Price Subject: Re: [PATCH] KVM: arm64: Prevent mixed-width VM creation In-Reply-To: <20210520124434.GD17233@C02TD0UTHF1T.local> References: <20210520122253.171545-1-maz@kernel.org> <20210520124434.GD17233@C02TD0UTHF1T.local> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kernel-team@android.com, stable@vger.kernel.org, steven.price@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Thu, 20 May 2021 13:44:34 +0100, Mark Rutland wrote: > > On Thu, May 20, 2021 at 01:22:53PM +0100, Marc Zyngier wrote: > > It looks like we have tolerated creating mixed-width VMs since... > > forever. However, that was never the intention, and we'd rather > > not have to support that pointless complexity. > > > > Forbid such a setup by making sure all the vcpus have the same > > register width. > > > > Reported-by: Steven Price > > Signed-off-by: Marc Zyngier > > Cc: stable@vger.kernel.org > > --- > > arch/arm64/kvm/reset.c | 28 ++++++++++++++++++++++++---- > > 1 file changed, 24 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > > index 956cdc240148..1cf308be6ef3 100644 > > --- a/arch/arm64/kvm/reset.c > > +++ b/arch/arm64/kvm/reset.c > > @@ -166,6 +166,25 @@ static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu) > > return 0; > > } > > > > +static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > > +{ > > + struct kvm_vcpu *tmp; > > + int i; > > + > > + /* Check that the vcpus are either all 32bit or all 64bit */ > > + kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > > + bool w; > > + > > + w = test_bit(KVM_ARM_VCPU_EL1_32BIT, tmp->arch.features); > > + w ^= test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features); > > + > > + if (w) > > + return false; > > + } > > I think this is wrong for a single-cpu VM. In that case, the loop will > have a single iteration, and tmp == vcpu, so w must be 0 regardless of > the value of arch.features. I don't immediately see what is wrong with a single-cpu VM. 'w' will be zero indeed, and we'll return that this is allowed. After all, each VM starts by being a single-CPU VM. But of course... > IIUC that doesn't prevent KVM_ARM_VCPU_EL1_32BIT being set when we don't > have the ARM64_HAS_32BIT_EL1 cap, unless that's checked elsewhere? ... I mistakenly removed the check against ARM64_HAS_32BIT_EL1... > > How about something like: > > | static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > | { > | bool is_32bit = vcpu_features_32bit(vcpu); > | struct kvm_vcpu *tmp; > | int i; > | > | if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is_32bit) > | return false; > | > | kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > | if (is_32bit != vcpu_features_32bit(tmp)) > | return false; > | } > | > | return true; > | } > > ... with a helper in like: > > | static bool vcpu_features_32bit(struct kvm_vcpu *vcpu) > | { > | return test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features); > | } > > ... or > > | static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature) > | { > | return test_bit(feature, vcpu->arch.features); > | } > > ... so that we can avoid the line splitting required by the length of > the test_bit() expression? Yup, looks OK to me (with a preference for the latter). Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB882C433B4 for ; Thu, 20 May 2021 12:59:03 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 32EA1613BA for ; Thu, 20 May 2021 12:59:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 32EA1613BA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id CA38F4B2A1; Thu, 20 May 2021 08:59:02 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zuqUs9LN+9xB; Thu, 20 May 2021 08:59:01 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A65864B491; Thu, 20 May 2021 08:59:01 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 939024B485 for ; Thu, 20 May 2021 08:59:00 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t1bgV1bhHmRN for ; Thu, 20 May 2021 08:58:59 -0400 (EDT) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 6AE884B2A1 for ; Thu, 20 May 2021 08:58:59 -0400 (EDT) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7DDC261004; Thu, 20 May 2021 12:58:58 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ljiGO-002aDT-6Q; Thu, 20 May 2021 13:58:56 +0100 Date: Thu, 20 May 2021 13:58:55 +0100 Message-ID: <87zgwptvcg.wl-maz@kernel.org> From: Marc Zyngier To: Mark Rutland Subject: Re: [PATCH] KVM: arm64: Prevent mixed-width VM creation In-Reply-To: <20210520124434.GD17233@C02TD0UTHF1T.local> References: <20210520122253.171545-1-maz@kernel.org> <20210520124434.GD17233@C02TD0UTHF1T.local> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kernel-team@android.com, stable@vger.kernel.org, steven.price@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: stable@vger.kernel.org, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Steven Price X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, 20 May 2021 13:44:34 +0100, Mark Rutland wrote: > > On Thu, May 20, 2021 at 01:22:53PM +0100, Marc Zyngier wrote: > > It looks like we have tolerated creating mixed-width VMs since... > > forever. However, that was never the intention, and we'd rather > > not have to support that pointless complexity. > > > > Forbid such a setup by making sure all the vcpus have the same > > register width. > > > > Reported-by: Steven Price > > Signed-off-by: Marc Zyngier > > Cc: stable@vger.kernel.org > > --- > > arch/arm64/kvm/reset.c | 28 ++++++++++++++++++++++++---- > > 1 file changed, 24 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > > index 956cdc240148..1cf308be6ef3 100644 > > --- a/arch/arm64/kvm/reset.c > > +++ b/arch/arm64/kvm/reset.c > > @@ -166,6 +166,25 @@ static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu) > > return 0; > > } > > > > +static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > > +{ > > + struct kvm_vcpu *tmp; > > + int i; > > + > > + /* Check that the vcpus are either all 32bit or all 64bit */ > > + kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > > + bool w; > > + > > + w = test_bit(KVM_ARM_VCPU_EL1_32BIT, tmp->arch.features); > > + w ^= test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features); > > + > > + if (w) > > + return false; > > + } > > I think this is wrong for a single-cpu VM. In that case, the loop will > have a single iteration, and tmp == vcpu, so w must be 0 regardless of > the value of arch.features. I don't immediately see what is wrong with a single-cpu VM. 'w' will be zero indeed, and we'll return that this is allowed. After all, each VM starts by being a single-CPU VM. But of course... > IIUC that doesn't prevent KVM_ARM_VCPU_EL1_32BIT being set when we don't > have the ARM64_HAS_32BIT_EL1 cap, unless that's checked elsewhere? ... I mistakenly removed the check against ARM64_HAS_32BIT_EL1... > > How about something like: > > | static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > | { > | bool is_32bit = vcpu_features_32bit(vcpu); > | struct kvm_vcpu *tmp; > | int i; > | > | if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is_32bit) > | return false; > | > | kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > | if (is_32bit != vcpu_features_32bit(tmp)) > | return false; > | } > | > | return true; > | } > > ... with a helper in like: > > | static bool vcpu_features_32bit(struct kvm_vcpu *vcpu) > | { > | return test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features); > | } > > ... or > > | static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature) > | { > | return test_bit(feature, vcpu->arch.features); > | } > > ... so that we can avoid the line splitting required by the length of > the test_bit() expression? Yup, looks OK to me (with a preference for the latter). Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4399EC433ED for ; Thu, 20 May 2021 13:03:01 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C068D611AD for ; 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Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1ljiGR-00GLg0-Ao for linux-arm-kernel@lists.infradead.org; Thu, 20 May 2021 12:59:00 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7DDC261004; Thu, 20 May 2021 12:58:58 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ljiGO-002aDT-6Q; Thu, 20 May 2021 13:58:56 +0100 Date: Thu, 20 May 2021 13:58:55 +0100 Message-ID: <87zgwptvcg.wl-maz@kernel.org> From: Marc Zyngier To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kernel-team@android.com, stable@vger.kernel.org, Steven Price Subject: Re: [PATCH] KVM: arm64: Prevent mixed-width VM creation In-Reply-To: <20210520124434.GD17233@C02TD0UTHF1T.local> References: <20210520122253.171545-1-maz@kernel.org> <20210520124434.GD17233@C02TD0UTHF1T.local> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kernel-team@android.com, stable@vger.kernel.org, steven.price@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210520_055859_429034_7CA76741 X-CRM114-Status: GOOD ( 33.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 20 May 2021 13:44:34 +0100, Mark Rutland wrote: > > On Thu, May 20, 2021 at 01:22:53PM +0100, Marc Zyngier wrote: > > It looks like we have tolerated creating mixed-width VMs since... > > forever. However, that was never the intention, and we'd rather > > not have to support that pointless complexity. > > > > Forbid such a setup by making sure all the vcpus have the same > > register width. > > > > Reported-by: Steven Price > > Signed-off-by: Marc Zyngier > > Cc: stable@vger.kernel.org > > --- > > arch/arm64/kvm/reset.c | 28 ++++++++++++++++++++++++---- > > 1 file changed, 24 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > > index 956cdc240148..1cf308be6ef3 100644 > > --- a/arch/arm64/kvm/reset.c > > +++ b/arch/arm64/kvm/reset.c > > @@ -166,6 +166,25 @@ static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu) > > return 0; > > } > > > > +static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > > +{ > > + struct kvm_vcpu *tmp; > > + int i; > > + > > + /* Check that the vcpus are either all 32bit or all 64bit */ > > + kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > > + bool w; > > + > > + w = test_bit(KVM_ARM_VCPU_EL1_32BIT, tmp->arch.features); > > + w ^= test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features); > > + > > + if (w) > > + return false; > > + } > > I think this is wrong for a single-cpu VM. In that case, the loop will > have a single iteration, and tmp == vcpu, so w must be 0 regardless of > the value of arch.features. I don't immediately see what is wrong with a single-cpu VM. 'w' will be zero indeed, and we'll return that this is allowed. After all, each VM starts by being a single-CPU VM. But of course... > IIUC that doesn't prevent KVM_ARM_VCPU_EL1_32BIT being set when we don't > have the ARM64_HAS_32BIT_EL1 cap, unless that's checked elsewhere? ... I mistakenly removed the check against ARM64_HAS_32BIT_EL1... > > How about something like: > > | static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > | { > | bool is_32bit = vcpu_features_32bit(vcpu); > | struct kvm_vcpu *tmp; > | int i; > | > | if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is_32bit) > | return false; > | > | kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > | if (is_32bit != vcpu_features_32bit(tmp)) > | return false; > | } > | > | return true; > | } > > ... with a helper in like: > > | static bool vcpu_features_32bit(struct kvm_vcpu *vcpu) > | { > | return test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features); > | } > > ... or > > | static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature) > | { > | return test_bit(feature, vcpu->arch.features); > | } > > ... so that we can avoid the line splitting required by the length of > the test_bit() expression? Yup, looks OK to me (with a preference for the latter). Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel