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Fri, 16 Nov 2018 00:30:47 -0800 (PST) Subject: Re: [PATCH 0/2] Meson8b: fixes for the cpu_scale_div clock From: Neil Armstrong To: Martin Blumenstingl , linux-amlogic@lists.infradead.org, jbrunet@baylibre.com Cc: linux-clk@vger.kernel.org, carlo@caione.org References: <20180927085921.24627-1-martin.blumenstingl@googlemail.com> Openpgp: preference=signencrypt Autocrypt: addr=narmstrong@baylibre.com; prefer-encrypt=mutual; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKE5laWwgQXJtc3Ryb25nIDxuYXJtc3Ryb25nQGJheWxpYnJlLmNvbT7CwHsEEwEKACUC GyMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheABQJXDO2CAhkBAAoJEBaat7Gkz/iubGIH/iyk RqvgB62oKOFlgOTYCMkYpm2aAOZZLf6VKHKc7DoVwuUkjHfIRXdslbrxi4pk5VKU6ZP9AKsN NtMZntB8WrBTtkAZfZbTF7850uwd3eU5cN/7N1Q6g0JQihE7w4GlIkEpQ8vwSg5W7hkx3yQ6 2YzrUZh/b7QThXbNZ7xOeSEms014QXazx8+txR7jrGF3dYxBsCkotO/8DNtZ1R+aUvRfpKg5 ZgABTC0LmAQnuUUf2PHcKFAHZo5KrdO+tyfL+LgTUXIXkK+tenkLsAJ0cagz1EZ5gntuheLD YJuzS4zN+1Asmb9kVKxhjSQOcIh6g2tw7vaYJgL/OzJtZi6JlIXOwE0ETVkGzwEIALyKDN/O GURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYpQTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXM coJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hi SvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY4yG6xI99NIPEVE9lNBXBKIlewIyVlkOa YvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoMMtsyw18YoX9BqMFInxqYQQ3j/HpVgTSv mo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUXoUk33HEAEQEAAcLAXwQYAQIACQUCTVkG zwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfnM7IbRuiSZS1unlySUVYu3SD6YBYnNi3G 5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa33eDIHu/zr1HMKErm+2SD6PO9umRef8V8 2o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCSKmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+ RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJ C3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTTQbM0WUIBIcGmq38+OgUsMYu4NzLu7uZF Acmp6h8g Organization: Baylibre Message-ID: <88485943-55a8-e045-b633-e33d7c352626@baylibre.com> Date: Fri, 16 Nov 2018 09:30:46 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 08/11/2018 15:16, Neil Armstrong wrote: > On 27/09/2018 10:59, Martin Blumenstingl wrote: >> While trying to add support for the TWD timer I found that our CPU clock >> calculation (when running off the "cpu_scale_div clock) is incorrect. >> >> The main problem was the cpu_scale_div clock: >> it's divider table has an off-by-one error. the old formula was: >> parent_rate / 2 * register_value >> however, testing shows that the correct formula is: >> parent_rate / 2 * (register value + 1) >> See the commit message of patch #1 for a complete description of the >> problem and it's history. >> >> While looking at the "cpu_scale_div" clock I also found that it's >> register width was also off-by-one, so this is fixed in a separate patch >> as well. >> >> Both patches are not critical because I haven't seen a case where u-boot >> uses cpu_scale_div for the CPU clock. It's only a problem when playing >> with the CPU clock in u-boot (by writing registers manually) or as soon >> as we support CPU frequency scaling. >> >> >> Martin Blumenstingl (2): >> clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table >> clk: meson: meson8b: fix the width of the cpu_scale_div clock >> >> drivers/clk/meson/meson8b.c | 17 +++++++++-------- >> 1 file changed, 9 insertions(+), 8 deletions(-) >> > > Pushed to fixes/drivers for 4.20 > > Neil > Finally, pushed to next/drivers to since these are not critical and to satisfy the dependencies of "Meson8b: make the CPU clock mutable" patchset. From mboxrd@z Thu Jan 1 00:00:00 1970 From: narmstrong@baylibre.com (Neil Armstrong) Date: Fri, 16 Nov 2018 09:30:46 +0100 Subject: [PATCH 0/2] Meson8b: fixes for the cpu_scale_div clock In-Reply-To: References: <20180927085921.24627-1-martin.blumenstingl@googlemail.com> Message-ID: <88485943-55a8-e045-b633-e33d7c352626@baylibre.com> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org On 08/11/2018 15:16, Neil Armstrong wrote: > On 27/09/2018 10:59, Martin Blumenstingl wrote: >> While trying to add support for the TWD timer I found that our CPU clock >> calculation (when running off the "cpu_scale_div clock) is incorrect. >> >> The main problem was the cpu_scale_div clock: >> it's divider table has an off-by-one error. the old formula was: >> parent_rate / 2 * register_value >> however, testing shows that the correct formula is: >> parent_rate / 2 * (register value + 1) >> See the commit message of patch #1 for a complete description of the >> problem and it's history. >> >> While looking at the "cpu_scale_div" clock I also found that it's >> register width was also off-by-one, so this is fixed in a separate patch >> as well. >> >> Both patches are not critical because I haven't seen a case where u-boot >> uses cpu_scale_div for the CPU clock. It's only a problem when playing >> with the CPU clock in u-boot (by writing registers manually) or as soon >> as we support CPU frequency scaling. >> >> >> Martin Blumenstingl (2): >> clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table >> clk: meson: meson8b: fix the width of the cpu_scale_div clock >> >> drivers/clk/meson/meson8b.c | 17 +++++++++-------- >> 1 file changed, 9 insertions(+), 8 deletions(-) >> > > Pushed to fixes/drivers for 4.20 > > Neil > Finally, pushed to next/drivers to since these are not critical and to satisfy the dependencies of "Meson8b: make the CPU clock mutable" patchset.