From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Date: Mon, 6 Nov 2017 13:12:41 +0100 Subject: [U-Boot] [PATCH 09/40] arm64: zynqmp: Update the GPU address size In-Reply-To: References: Message-ID: <88c67160289687911d0f2ce464f600fe06dc483b.1509970359.git.michal.simek@xilinx.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Hyun Kwon The correct register size is 0x10000, otherwise it overlaps with other register space. Signed-off-by: Hyun Kwon Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 4d4d62f4930d..1be4d2c68001 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -470,7 +470,7 @@ gpu: gpu at fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; - reg = <0x0 0xfd4b0000 0x0 0x30000>; + reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; -- 1.9.1