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(p200300d82f249200124ef0bf6f8ccbd8.dip0.t-ipconnect.de. [2003:d8:2f24:9200:124e:f0bf:6f8c:cbd8]) by smtp.gmail.com with ESMTPSA id i35-20020adf90a6000000b00203e767a1d2sm4123361wri.103.2022.03.18.02.59.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Mar 2022 02:59:12 -0700 (PDT) Message-ID: <8989a07b-3a5b-0c81-983f-b35403d19579@redhat.com> Date: Fri, 18 Mar 2022 10:59:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v1 4/7] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Content-Language: en-US To: Catalin Marinas Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , Linus Torvalds , David Rientjes , Shakeel Butt , John Hubbard , Jason Gunthorpe , Mike Kravetz , Mike Rapoport , Yang Shi , "Kirill A . Shutemov" , Matthew Wilcox , Vlastimil Babka , Jann Horn , Michal Hocko , Nadav Amit , Rik van Riel , Roman Gushchin , Andrea Arcangeli , Peter Xu , Donald Dutile , Christoph Hellwig , Oleg Nesterov , Jan Kara , Liang Zhang , Pedro Gomes , Oded Gabbay , Will Deacon , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-5-david@redhat.com> From: David Hildenbrand Organization: Red Hat In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17.03.22 18:58, Catalin Marinas wrote: > On Thu, Mar 17, 2022 at 11:04:18AM +0100, David Hildenbrand wrote: >> On 16.03.22 19:27, Catalin Marinas wrote: >>> On Tue, Mar 15, 2022 at 03:18:34PM +0100, David Hildenbrand wrote: >>>> @@ -909,12 +925,13 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, >>>> /* >>>> * Encode and decode a swap entry: >>>> * bits 0-1: present (must be zero) >>>> - * bits 2-7: swap type >>>> + * bits 2: remember PG_anon_exclusive >>>> + * bits 3-7: swap type >>>> * bits 8-57: swap offset >>>> * bit 58: PTE_PROT_NONE (must be zero) >>> >>> I don't remember exactly why we reserved bits 0 and 1 when, from the >>> hardware perspective, it's sufficient for bit 0 to be 0 and the whole >>> pte becomes invalid. We use bit 1 as the 'table' bit (when 0 at pmd >>> level, it's a huge page) but we shouldn't check for this on a swap >>> entry. >> >> You mean >> >> arch/arm64/include/asm/pgtable-hwdef.h:#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) >> >> right? > > Yes. > >> I wonder why it even exists, for arm64 I only spot: >> >> arch/arm64/include/asm/pgtable.h:#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) >> >> I don't really see code that sets PTE_TABLE_BIT. >> >> Similarly, I don't see code that sets PMD_TABLE_BIT/PUD_TABLE_BIT/P4D_TABLE_BIT. >> Most probably setting code is not using the defines, that's why I'm not finding it. > > It gets set as part of P*D_TYPE_TABLE via p*d_populate(). We use the > P*D_TABLE_BIT mostly for checking whether it's a huge page or not (the > arm64 hugetlbpage.c code). > Makes sense, after digging into the arm arm, I agree that it should be safe to reuse bit 1. I'll use this (yet untested) patch in v2: >From a48d08339574b7c42e0b032f0fc334872591744c Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 17 Mar 2022 11:46:26 +0100 Subject: [PATCH] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Let's use bit 1, which should be irrelevant if the PTE is marked invalid eiher way -- we really only care about bit 0. Note that one alternative would be using one of the type bits: core-mm only supports 5 bits, so there is no need to reserve space for 6. Signed-off-by: David Hildenbrand --- arch/arm64/include/asm/pgtable-prot.h | 1 + arch/arm64/include/asm/pgtable.h | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h index b1e1b74d993c..fd6ddf14c190 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -14,6 +14,7 @@ * Software defined PTE bits definition. */ #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ +#define PTE_SWP_EXCLUSIVE (PTE_TABLE_BIT) /* only for swp ptes */ #define PTE_DIRTY (_AT(pteval_t, 1) << 55) #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) #define PTE_DEVMAP (_AT(pteval_t, 1) << 57) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 94e147e5456c..c78994073cd0 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -402,6 +402,22 @@ static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); } +#define __HAVE_ARCH_PTE_SWP_EXCLUSIVE +static inline pte_t pte_swp_mkexclusive(pte_t pte) +{ + return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); +} + +static inline int pte_swp_exclusive(pte_t pte) +{ + return pte_val(pte) & PTE_SWP_EXCLUSIVE; +} + +static inline pte_t pte_swp_clear_exclusive(pte_t pte) +{ + return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); +} + #ifdef CONFIG_NUMA_BALANCING /* * See the comment in include/linux/pgtable.h @@ -908,7 +924,8 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, /* * Encode and decode a swap entry: - * bits 0-1: present (must be zero) + * bits 0: present (must be zero) + * bits 1: remember PG_anon_exclusive * bits 2-7: swap type * bits 8-57: swap offset * bit 58: PTE_PROT_NONE (must be zero) -- 2.35.1 -- Thanks, David / dhildenb From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20DEBC433FE for ; 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[2003:d8:2f24:9200:124e:f0bf:6f8c:cbd8]) by smtp.gmail.com with ESMTPSA id i35-20020adf90a6000000b00203e767a1d2sm4123361wri.103.2022.03.18.02.59.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Mar 2022 02:59:12 -0700 (PDT) Message-ID: <8989a07b-3a5b-0c81-983f-b35403d19579@redhat.com> Date: Fri, 18 Mar 2022 10:59:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v1 4/7] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE To: Catalin Marinas References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-5-david@redhat.com> From: David Hildenbrand Organization: Red Hat In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: x86@kernel.org, Jan Kara , Yang Shi , Dave Hansen , Peter Xu , Michal Hocko , linux-mm@kvack.org, Donald Dutile , Liang Zhang , Borislav Petkov , Alexander Gordeev , Will Deacon , Christoph Hellwig , Paul Mackerras , Andrea Arcangeli , linux-s390@vger.kernel.org, Vasily Gorbik , Rik van Riel , Hugh Dickins , Matthew Wilcox , Mike Rapoport , Ingo Molnar , linux-arm-kernel@lists.infradead.org, Jason Gunthorpe , David Rientjes , Pedro Gomes , Jann Horn , John Hubbard , Heiko Carstens , Shakeel Butt , Oleg Nesterov , Thomas Gleixner , Vlastimil Babka , Oded Gabbay , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Nadav Amit , Andrew Morton , Linus Torvalds , Roman Gushchin , "Kirill A . Shutemov" , Mike Kravetz Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 17.03.22 18:58, Catalin Marinas wrote: > On Thu, Mar 17, 2022 at 11:04:18AM +0100, David Hildenbrand wrote: >> On 16.03.22 19:27, Catalin Marinas wrote: >>> On Tue, Mar 15, 2022 at 03:18:34PM +0100, David Hildenbrand wrote: >>>> @@ -909,12 +925,13 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, >>>> /* >>>> * Encode and decode a swap entry: >>>> * bits 0-1: present (must be zero) >>>> - * bits 2-7: swap type >>>> + * bits 2: remember PG_anon_exclusive >>>> + * bits 3-7: swap type >>>> * bits 8-57: swap offset >>>> * bit 58: PTE_PROT_NONE (must be zero) >>> >>> I don't remember exactly why we reserved bits 0 and 1 when, from the >>> hardware perspective, it's sufficient for bit 0 to be 0 and the whole >>> pte becomes invalid. We use bit 1 as the 'table' bit (when 0 at pmd >>> level, it's a huge page) but we shouldn't check for this on a swap >>> entry. >> >> You mean >> >> arch/arm64/include/asm/pgtable-hwdef.h:#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) >> >> right? > > Yes. > >> I wonder why it even exists, for arm64 I only spot: >> >> arch/arm64/include/asm/pgtable.h:#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) >> >> I don't really see code that sets PTE_TABLE_BIT. >> >> Similarly, I don't see code that sets PMD_TABLE_BIT/PUD_TABLE_BIT/P4D_TABLE_BIT. >> Most probably setting code is not using the defines, that's why I'm not finding it. > > It gets set as part of P*D_TYPE_TABLE via p*d_populate(). We use the > P*D_TABLE_BIT mostly for checking whether it's a huge page or not (the > arm64 hugetlbpage.c code). > Makes sense, after digging into the arm arm, I agree that it should be safe to reuse bit 1. I'll use this (yet untested) patch in v2: >From a48d08339574b7c42e0b032f0fc334872591744c Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 17 Mar 2022 11:46:26 +0100 Subject: [PATCH] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Let's use bit 1, which should be irrelevant if the PTE is marked invalid eiher way -- we really only care about bit 0. Note that one alternative would be using one of the type bits: core-mm only supports 5 bits, so there is no need to reserve space for 6. Signed-off-by: David Hildenbrand --- arch/arm64/include/asm/pgtable-prot.h | 1 + arch/arm64/include/asm/pgtable.h | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h index b1e1b74d993c..fd6ddf14c190 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -14,6 +14,7 @@ * Software defined PTE bits definition. */ #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ +#define PTE_SWP_EXCLUSIVE (PTE_TABLE_BIT) /* only for swp ptes */ #define PTE_DIRTY (_AT(pteval_t, 1) << 55) #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) #define PTE_DEVMAP (_AT(pteval_t, 1) << 57) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 94e147e5456c..c78994073cd0 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -402,6 +402,22 @@ static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); } +#define __HAVE_ARCH_PTE_SWP_EXCLUSIVE +static inline pte_t pte_swp_mkexclusive(pte_t pte) +{ + return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); +} + +static inline int pte_swp_exclusive(pte_t pte) +{ + return pte_val(pte) & PTE_SWP_EXCLUSIVE; +} + +static inline pte_t pte_swp_clear_exclusive(pte_t pte) +{ + return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); +} + #ifdef CONFIG_NUMA_BALANCING /* * See the comment in include/linux/pgtable.h @@ -908,7 +924,8 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, /* * Encode and decode a swap entry: - * bits 0-1: present (must be zero) + * bits 0: present (must be zero) + * bits 1: remember PG_anon_exclusive * bits 2-7: swap type * bits 8-57: swap offset * bit 58: PTE_PROT_NONE (must be zero) -- 2.35.1 -- Thanks, David / dhildenb From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46E64C433F5 for ; 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(p200300d82f249200124ef0bf6f8ccbd8.dip0.t-ipconnect.de. [2003:d8:2f24:9200:124e:f0bf:6f8c:cbd8]) by smtp.gmail.com with ESMTPSA id i35-20020adf90a6000000b00203e767a1d2sm4123361wri.103.2022.03.18.02.59.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Mar 2022 02:59:12 -0700 (PDT) Message-ID: <8989a07b-3a5b-0c81-983f-b35403d19579@redhat.com> Date: Fri, 18 Mar 2022 10:59:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v1 4/7] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE To: Catalin Marinas Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , Linus Torvalds , David Rientjes , Shakeel Butt , John Hubbard , Jason Gunthorpe , Mike Kravetz , Mike Rapoport , Yang Shi , "Kirill A . Shutemov" , Matthew Wilcox , Vlastimil Babka , Jann Horn , Michal Hocko , Nadav Amit , Rik van Riel , Roman Gushchin , Andrea Arcangeli , Peter Xu , Donald Dutile , Christoph Hellwig , Oleg Nesterov , Jan Kara , Liang Zhang , Pedro Gomes , Oded Gabbay , Will Deacon , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-5-david@redhat.com> From: David Hildenbrand Organization: Red Hat In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220318_025919_705864_5F3DB075 X-CRM114-Status: GOOD ( 29.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 17.03.22 18:58, Catalin Marinas wrote: > On Thu, Mar 17, 2022 at 11:04:18AM +0100, David Hildenbrand wrote: >> On 16.03.22 19:27, Catalin Marinas wrote: >>> On Tue, Mar 15, 2022 at 03:18:34PM +0100, David Hildenbrand wrote: >>>> @@ -909,12 +925,13 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, >>>> /* >>>> * Encode and decode a swap entry: >>>> * bits 0-1: present (must be zero) >>>> - * bits 2-7: swap type >>>> + * bits 2: remember PG_anon_exclusive >>>> + * bits 3-7: swap type >>>> * bits 8-57: swap offset >>>> * bit 58: PTE_PROT_NONE (must be zero) >>> >>> I don't remember exactly why we reserved bits 0 and 1 when, from the >>> hardware perspective, it's sufficient for bit 0 to be 0 and the whole >>> pte becomes invalid. We use bit 1 as the 'table' bit (when 0 at pmd >>> level, it's a huge page) but we shouldn't check for this on a swap >>> entry. >> >> You mean >> >> arch/arm64/include/asm/pgtable-hwdef.h:#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) >> >> right? > > Yes. > >> I wonder why it even exists, for arm64 I only spot: >> >> arch/arm64/include/asm/pgtable.h:#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) >> >> I don't really see code that sets PTE_TABLE_BIT. >> >> Similarly, I don't see code that sets PMD_TABLE_BIT/PUD_TABLE_BIT/P4D_TABLE_BIT. >> Most probably setting code is not using the defines, that's why I'm not finding it. > > It gets set as part of P*D_TYPE_TABLE via p*d_populate(). We use the > P*D_TABLE_BIT mostly for checking whether it's a huge page or not (the > arm64 hugetlbpage.c code). > Makes sense, after digging into the arm arm, I agree that it should be safe to reuse bit 1. I'll use this (yet untested) patch in v2: >From a48d08339574b7c42e0b032f0fc334872591744c Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 17 Mar 2022 11:46:26 +0100 Subject: [PATCH] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Let's use bit 1, which should be irrelevant if the PTE is marked invalid eiher way -- we really only care about bit 0. Note that one alternative would be using one of the type bits: core-mm only supports 5 bits, so there is no need to reserve space for 6. Signed-off-by: David Hildenbrand --- arch/arm64/include/asm/pgtable-prot.h | 1 + arch/arm64/include/asm/pgtable.h | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h index b1e1b74d993c..fd6ddf14c190 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -14,6 +14,7 @@ * Software defined PTE bits definition. */ #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ +#define PTE_SWP_EXCLUSIVE (PTE_TABLE_BIT) /* only for swp ptes */ #define PTE_DIRTY (_AT(pteval_t, 1) << 55) #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) #define PTE_DEVMAP (_AT(pteval_t, 1) << 57) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 94e147e5456c..c78994073cd0 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -402,6 +402,22 @@ static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); } +#define __HAVE_ARCH_PTE_SWP_EXCLUSIVE +static inline pte_t pte_swp_mkexclusive(pte_t pte) +{ + return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); +} + +static inline int pte_swp_exclusive(pte_t pte) +{ + return pte_val(pte) & PTE_SWP_EXCLUSIVE; +} + +static inline pte_t pte_swp_clear_exclusive(pte_t pte) +{ + return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); +} + #ifdef CONFIG_NUMA_BALANCING /* * See the comment in include/linux/pgtable.h @@ -908,7 +924,8 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, /* * Encode and decode a swap entry: - * bits 0-1: present (must be zero) + * bits 0: present (must be zero) + * bits 1: remember PG_anon_exclusive * bits 2-7: swap type * bits 8-57: swap offset * bit 58: PTE_PROT_NONE (must be zero) -- 2.35.1 -- Thanks, David / dhildenb _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel