From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:50668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UGTp9-0005av-7h for qemu-devel@nongnu.org; Fri, 15 Mar 2013 08:33:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UGTp5-0006tp-S7 for qemu-devel@nongnu.org; Fri, 15 Mar 2013 08:33:27 -0400 Mime-Version: 1.0 (Apple Message framework v1278) Content-Type: text/plain; charset=us-ascii From: Alexander Graf In-Reply-To: <1363226008-26639-6-git-send-email-david@gibson.dropbear.id.au> Date: Fri, 15 Mar 2013 13:33:18 +0100 Content-Transfer-Encoding: quoted-printable Message-Id: <89E98310-17EE-4BFD-B8F6-A8FCC23FE5F1@suse.de> References: <1363226008-26639-1-git-send-email-david@gibson.dropbear.id.au> <1363226008-26639-6-git-send-email-david@gibson.dropbear.id.au> Subject: Re: [Qemu-devel] [PATCH 5/5] pseries: Move XICS initialization before cpu initialization List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: Michael Ellerman , "qemu-ppc@nongnu.org list:PowerPC" , qemu-devel qemu-devel , Paul Mackerras On 14.03.2013, at 02:53, David Gibson wrote: > Currently, the pseries machine initializes the cpus, then the XICS > interrupt controller. However, to support the upcoming in-kernel XICS > implementation we will need to initialize the irq controller before = the > vcpus. This patch makes the necesssary rearrangement. This means the We're changing that notion in the in-kernel XICS discussions. The flow = will look like this: * create vcpus * create XICS * foreach (vcpu) * enable_cap(vcpu, CAP_XICS_SERVER, xics_handle) However, that means we still need to know the maximum number of = supported vcpus during the create phase. That number can be bigger than = smp_cpus though, since you probably want to support hotplug add of CPUs = later on. Can't we just make the number of supported "interrupt servers" a = constant? Alex > xics init code can no longer auto-detect the number of cpus = ("interrupt > servers" in XICS terminology) and so we must pass that in explicitly = from > the platform code. >=20 > Signed-off-by: Michael Ellerman > Signed-off-by: Ben Herrenschmidt > Signed-off-by: David Gibson > --- > hw/ppc/spapr.c | 12 +++++++----- > hw/ppc/xics.c | 57 = +++++++++++++++++++++++++------------------------------- > hw/xics.h | 3 ++- > 3 files changed, 34 insertions(+), 38 deletions(-) >=20 > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index 7293082..b2c9b42 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -791,6 +791,11 @@ static void ppc_spapr_init(QEMUMachineInitArgs = *args) > spapr->htab_shift++; > } >=20 > + /* Set up Interrupt Controller before we create the VCPUs */ > + spapr->icp =3D xics_system_init(smp_cpus * kvmppc_smt_threads() / = smp_threads, > + XICS_IRQS); > + spapr->next_irq =3D XICS_IRQ_BASE; > + > /* init CPUs */ > if (cpu_model =3D=3D NULL) { > cpu_model =3D kvm_enabled() ? "host" : "POWER7"; > @@ -803,6 +808,8 @@ static void ppc_spapr_init(QEMUMachineInitArgs = *args) > } > env =3D &cpu->env; >=20 > + xics_cpu_setup(spapr->icp, cpu); > + > /* Set time-base frequency to 512 MHz */ > cpu_ppc_tb_init(env, TIMEBASE_FREQ); >=20 > @@ -842,11 +849,6 @@ static void ppc_spapr_init(QEMUMachineInitArgs = *args) > } > g_free(filename); >=20 > - > - /* Set up Interrupt Controller */ > - spapr->icp =3D xics_system_init(XICS_IRQS); > - spapr->next_irq =3D XICS_IRQ_BASE; > - > /* Set up EPOW events infrastructure */ > spapr_events_init(spapr); >=20 > diff --git a/hw/ppc/xics.c b/hw/ppc/xics.c > index c3ef12f..374da5b 100644 > --- a/hw/ppc/xics.c > +++ b/hw/ppc/xics.c > @@ -521,45 +521,38 @@ static void xics_reset(void *opaque) > } > } >=20 > -struct icp_state *xics_system_init(int nr_irqs) > +void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu) > { > - CPUPPCState *env; > - CPUState *cpu; > - int max_server_num; > - struct icp_state *icp; > - struct ics_state *ics; > + CPUState *cs =3D CPU(cpu); > + CPUPPCState *env =3D &cpu->env; > + struct icp_server_state *ss =3D &icp->ss[cs->cpu_index]; >=20 > - max_server_num =3D -1; > - for (env =3D first_cpu; env !=3D NULL; env =3D env->next_cpu) { > - cpu =3D CPU(ppc_env_get_cpu(env)); > - if (cpu->cpu_index > max_server_num) { > - max_server_num =3D cpu->cpu_index; > - } > - } > + assert(cs->cpu_index < icp->nr_servers); >=20 > - icp =3D g_malloc0(sizeof(*icp)); > - icp->nr_servers =3D max_server_num + 1; > - icp->ss =3D g_malloc0(icp->nr_servers*sizeof(struct = icp_server_state)); > + switch (PPC_INPUT(env)) { > + case PPC_FLAGS_INPUT_POWER7: > + ss->output =3D env->irq_inputs[POWER7_INPUT_INT]; > + break; >=20 > - for (env =3D first_cpu; env !=3D NULL; env =3D env->next_cpu) { > - cpu =3D CPU(ppc_env_get_cpu(env)); > - struct icp_server_state *ss =3D &icp->ss[cpu->cpu_index]; > + case PPC_FLAGS_INPUT_970: > + ss->output =3D env->irq_inputs[PPC970_INPUT_INT]; > + break; >=20 > - switch (PPC_INPUT(env)) { > - case PPC_FLAGS_INPUT_POWER7: > - ss->output =3D env->irq_inputs[POWER7_INPUT_INT]; > - break; > + default: > + fprintf(stderr, "XICS interrupt controller does not support = this CPU " > + "bus model\n"); > + abort(); > + } > +} >=20 > - case PPC_FLAGS_INPUT_970: > - ss->output =3D env->irq_inputs[PPC970_INPUT_INT]; > - break; > +struct icp_state *xics_system_init(int nr_servers, int nr_irqs) > +{ > + struct icp_state *icp; > + struct ics_state *ics; >=20 > - default: > - hw_error("XICS interrupt model does not support this CPU = bus " > - "model\n"); > - exit(1); > - } > - } > + icp =3D g_malloc0(sizeof(*icp)); > + icp->nr_servers =3D nr_servers; > + icp->ss =3D g_malloc0(icp->nr_servers*sizeof(struct = icp_server_state)); >=20 > ics =3D g_malloc0(sizeof(*ics)); > ics->nr_irqs =3D nr_irqs; > diff --git a/hw/xics.h b/hw/xics.h > index c3bf008..6bce042 100644 > --- a/hw/xics.h > +++ b/hw/xics.h > @@ -35,6 +35,7 @@ struct icp_state; > qemu_irq xics_get_qirq(struct icp_state *icp, int irq); > void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi); >=20 > -struct icp_state *xics_system_init(int nr_irqs); > +struct icp_state *xics_system_init(int nr_servers, int nr_irqs); > +void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu); >=20 > #endif /* __XICS_H__ */ > --=20 > 1.7.10.4 >=20