From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E653BC433FE for ; Thu, 16 Sep 2021 09:03:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF59D61164 for ; Thu, 16 Sep 2021 09:03:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236335AbhIPJFG (ORCPT ); Thu, 16 Sep 2021 05:05:06 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:59897 "EHLO out1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236186AbhIPJEw (ORCPT ); Thu, 16 Sep 2021 05:04:52 -0400 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id CBDB55C0213; Thu, 16 Sep 2021 05:03:31 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Thu, 16 Sep 2021 05:03:31 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm3; bh=GZkDga 6ssumhZQoFHGM4sdNqFoaPvBwApjIOon26ucg=; b=n0yZM/AuhRj4N4gfKHS277 m7MmBUKdaLG9mTTqPr5Sg8ZFTOudNnok9diINmwxEmpCiLv+Pj4yXWcz7vVSEeRF +MmxddbSIeYVAtDbf3aVo8gukiOKKPQfW8te9RZ+FRbYRGGDu7C7pkbScGLR6ua/ MNDlgwRx/R0UOytYssml/0iEqGN3mew3BUxKcn88hZra1JqoJQvS6HLopyIrHrsA GA7WK0zrdKjGY3ANcgGexqo6ARTFXtQmDY7PtkB6fc3uZLu7Pik8Nqz+RWVo8gUf MSt8S06BW+Q5h/wTcQyZbHAqsCs5PHMXdN7gypEZV9EnklBshh7d+KFXusbLIzBw == X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudehgedgtdeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepfffhvffujgfkfhggtgesthdtredttddtvdenucfhrhhomhephfhinhhnucfv hhgrihhnuceofhhthhgrihhnsehlihhnuhigqdhmieekkhdrohhrgheqnecuggftrfgrth htvghrnhepveefvddvhfeuvdeigfffteehvdeiheegjeeuheekudegjeefffeludekffei gedvnecuffhomhgrihhnpehngihprdgtohhmnecuvehluhhsthgvrhfuihiivgeptdenuc frrghrrghmpehmrghilhhfrhhomhepfhhthhgrihhnsehlihhnuhigqdhmieekkhdrohhr gh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 16 Sep 2021 05:03:28 -0400 (EDT) Date: Thu, 16 Sep 2021 19:03:15 +1000 (AEST) From: Finn Thain To: Al Viro cc: linux-m68k@lists.linux-m68k.org, Geert Uytterhoeven , Greg Ungerer , linux-kernel@vger.kernel.org Subject: Re: [RFC][CFT] signal handling fixes In-Reply-To: Message-ID: <89b7f0e5-21a5-5828-1eb8-5119fb8e2d58@linux-m68k.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 25 Jul 2021, Al Viro wrote: > ... > > PS: FWIW, ifdefs in arch/m68k/kernel/signal.c are wrong - it's not !MMU > vs. coldfire/MMU vs. classic/MMU. It's actually 68000 vs. coldfire vs. > everything else. These days it's nearly correct, but only because on > MMU variants of coldfire we never see exception stack frames with type > other than 4 - it's controlled by alignment of kernel stack pointer on > those, and it's under the kernel control, so it's always 32bit-aligned. > It used to be more serious back when we had 68360 support - that's !MMU > and exception stack frames are like those on 68020, unless I'm > misreading their manual... > I don't claim to understand this code but CPU32 cores appear to be unsupported on either #ifdef branch: the MMU branch due to CACR and CAAR used in push_cache(), and the !MMU branch due to frame format $4 used in adjust_format(). The CPU32 Reference Manual appendix says these chips only supports control registers SFC, DFC, VBR and stack frame formats $0, $2, $C. https://www.nxp.com/files-static/microcontrollers/doc/ref_manual/CPU32RM.pdf