From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH] drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY Date: Mon, 20 May 2019 21:35:16 +0000 Message-ID: <89db60dcd125b9ac02fd1a79550715ae907418ab.camel@intel.com> References: <20190520045646.27055-1-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0616656277==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0EF1188FA1 for ; Mon, 20 May 2019 21:35:17 +0000 (UTC) In-Reply-To: <20190520045646.27055-1-rodrigo.vivi@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Vivi, Rodrigo" , "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org --===============0616656277== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-shUslvaN+WZb922gmiRW" --=-shUslvaN+WZb922gmiRW Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sun, 2019-05-19 at 21:56 -0700, Rodrigo Vivi wrote: > Suspend resume is broken if we try to enable/disable dc9 on > cases with disabled displays. >=20 Reviewed-by: Jos=C3=A9 Roberto de Souza > Cc: Jos=C3=A9 Roberto de Souza > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_drv.c | 103 ++++++++++++++++++++++------ > ---- > 1 file changed, 71 insertions(+), 32 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_drv.c > b/drivers/gpu/drm/i915/i915_drv.c > index 2c7a4318d13c..90693327065a 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -2117,6 +2117,15 @@ get_suspend_mode(struct drm_i915_private > *dev_priv, bool hibernate) > return I915_DRM_SUSPEND_MEM; > } > =20 > +static void intel_display_suspend_late(struct drm_i915_private > *dev_priv) > +{ > + if (!HAS_DISPLAY(dev_priv)) > + return; > + > + if (INTEL_GEN(dev_priv) >=3D 11 || IS_GEN9_LP(dev_priv)) > + bxt_enable_dc9(dev_priv); > +} > + > static int i915_drm_suspend_late(struct drm_device *dev, bool > hibernation) > { > struct drm_i915_private *dev_priv =3D to_i915(dev); > @@ -2132,10 +2141,10 @@ static int i915_drm_suspend_late(struct > drm_device *dev, bool hibernation) > intel_power_domains_suspend(dev_priv, > get_suspend_mode(dev_priv, > hibernation)); > =20 > + intel_display_suspend_late(dev_priv); > + > ret =3D 0; > - if (INTEL_GEN(dev_priv) >=3D 11 || IS_GEN9_LP(dev_priv)) > - bxt_enable_dc9(dev_priv); > - else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > hsw_enable_pc8(dev_priv); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > ret =3D vlv_suspend_complete(dev_priv); > @@ -2265,6 +2274,17 @@ static int i915_drm_resume(struct drm_device > *dev) > return 0; > } > =20 > +static void intel_display_resume_early(struct drm_i915_private > *dev_priv) > +{ > + if (!HAS_DISPLAY(dev_priv)) > + return; > + > + if (INTEL_GEN(dev_priv) >=3D 11 || IS_GEN9_LP(dev_priv)) { > + gen9_sanitize_dc_state(dev_priv); > + bxt_disable_dc9(dev_priv); > + } > +} > + > static int i915_drm_resume_early(struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D to_i915(dev); > @@ -2327,10 +2347,9 @@ static int i915_drm_resume_early(struct > drm_device *dev) > =20 > i915_check_and_clear_faults(dev_priv); > =20 > - if (INTEL_GEN(dev_priv) >=3D 11 || IS_GEN9_LP(dev_priv)) { > - gen9_sanitize_dc_state(dev_priv); > - bxt_disable_dc9(dev_priv); > - } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > + intel_display_resume_early(dev_priv); > + > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > hsw_disable_pc8(dev_priv); > } > =20 > @@ -2868,6 +2887,20 @@ static int vlv_resume_prepare(struct > drm_i915_private *dev_priv, > return ret; > } > =20 > +static void intel_runtime_display_suspend(struct drm_i915_private > *dev_priv) > +{ > + if (!HAS_DISPLAY(dev_priv)) > + return; > + > + if (INTEL_GEN(dev_priv) >=3D 11) { > + icl_display_core_uninit(dev_priv); > + bxt_enable_dc9(dev_priv); > + } else if (IS_GEN9_LP(dev_priv)) { > + bxt_display_core_uninit(dev_priv); > + bxt_enable_dc9(dev_priv); > + } > +} > + > static int intel_runtime_suspend(struct device *kdev) > { > struct pci_dev *pdev =3D to_pci_dev(kdev); > @@ -2897,14 +2930,10 @@ static int intel_runtime_suspend(struct > device *kdev) > =20 > intel_uncore_suspend(&dev_priv->uncore); > =20 > + intel_runtime_display_suspend(dev_priv); > + > ret =3D 0; > - if (INTEL_GEN(dev_priv) >=3D 11) { > - icl_display_core_uninit(dev_priv); > - bxt_enable_dc9(dev_priv); > - } else if (IS_GEN9_LP(dev_priv)) { > - bxt_display_core_uninit(dev_priv); > - bxt_enable_dc9(dev_priv); > - } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > hsw_enable_pc8(dev_priv); > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > { > ret =3D vlv_suspend_complete(dev_priv); > @@ -2966,6 +2995,31 @@ static int intel_runtime_suspend(struct device > *kdev) > return 0; > } > =20 > +static void intel_runtime_display_resume(struct drm_i915_private > *dev_priv) > +{ > + if (!HAS_DISPLAY(dev_priv)) > + return; > + > + if (INTEL_GEN(dev_priv) >=3D 11) { > + bxt_disable_dc9(dev_priv); > + icl_display_core_init(dev_priv, true); > + if (dev_priv->csr.dmc_payload) { > + if (dev_priv->csr.allowed_dc_mask & > + DC_STATE_EN_UPTO_DC6) > + skl_enable_dc6(dev_priv); > + else if (dev_priv->csr.allowed_dc_mask & > + DC_STATE_EN_UPTO_DC5) > + gen9_enable_dc5(dev_priv); > + } > + } else if (IS_GEN9_LP(dev_priv)) { > + bxt_disable_dc9(dev_priv); > + bxt_display_core_init(dev_priv, true); > + if (dev_priv->csr.dmc_payload && > + (dev_priv->csr.allowed_dc_mask & > DC_STATE_EN_UPTO_DC5)) > + gen9_enable_dc5(dev_priv); > + } > +} > + > static int intel_runtime_resume(struct device *kdev) > { > struct pci_dev *pdev =3D to_pci_dev(kdev); > @@ -2986,24 +3040,9 @@ static int intel_runtime_resume(struct device > *kdev) > if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) > DRM_DEBUG_DRIVER("Unclaimed access during suspend, > bios?\n"); > =20 > - if (INTEL_GEN(dev_priv) >=3D 11) { > - bxt_disable_dc9(dev_priv); > - icl_display_core_init(dev_priv, true); > - if (dev_priv->csr.dmc_payload) { > - if (dev_priv->csr.allowed_dc_mask & > - DC_STATE_EN_UPTO_DC6) > - skl_enable_dc6(dev_priv); > - else if (dev_priv->csr.allowed_dc_mask & > - DC_STATE_EN_UPTO_DC5) > - gen9_enable_dc5(dev_priv); > - } > - } else if (IS_GEN9_LP(dev_priv)) { > - bxt_disable_dc9(dev_priv); > - bxt_display_core_init(dev_priv, true); > - if (dev_priv->csr.dmc_payload && > - (dev_priv->csr.allowed_dc_mask & > DC_STATE_EN_UPTO_DC5)) > - gen9_enable_dc5(dev_priv); > - } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > + intel_runtime_display_resume(dev_priv); > + > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > hsw_disable_pc8(dev_priv); > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > { > ret =3D vlv_resume_prepare(dev_priv, true); --=-shUslvaN+WZb922gmiRW Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlzjHZQACgkQVenbO/mO WkldjwgAhTO1BUy1S2hScsBlG0fchi9gYk/qDZC2IAc/Ilcv0wRbAukuxYe6ZY21 ITDcU/xDheqSOVH/gEn7HCel2+OfTn39z9wsF1ifAlwGoup+53xnSDz+f5m4fXOX TrvqG4yyFFSsipE5o4yNz3Im1fsWl5dKLXuoHASZCosaWcsbFrey02MqH6OYnLUG gb3svTl5Qa4d3H9YwK9KLxvh9d6FOsCTv/viRblE52oZnIbwcXQy0eUpliGsKF9o QJzFcyv9x+FT0forbJFMuDG3+OzKDGJ9kLoth3tCDFWQ/6fECopxV7wZefQz6hQS 1cpLxFFfJeFdi+GbLsp3O0sx1eywUg== =+iJA -----END PGP SIGNATURE----- --=-shUslvaN+WZb922gmiRW-- --===============0616656277== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 --===============0616656277==--