From: Rebecca Cran <rebecca@nuviainc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Richard Henderson <richard.henderson@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 1/2] target/arm: add support for FEAT_DIT, Data Independent Timing
Date: Mon, 14 Dec 2020 11:11:46 -0700 [thread overview]
Message-ID: <8aacc648-c550-c5a9-eed1-5031cb95a5fd@nuviainc.com> (raw)
In-Reply-To: <CAFEAcA9NOez16SaKsegpURPtMJDByYQ2MaeUKjQAiKhm=O-7LA@mail.gmail.com>
On 12/11/20 2:37 PM, Peter Maydell wrote:
> On Fri, 11 Dec 2020 at 19:51, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> I'll let Peter weigh in, but I think it makes sense to move the SS bit
>> somewhere else (e.g. env->pstate) and merge it into SPSR_ELx upon interrupt.
>> While what we're doing here is convenient, it's not architectural, and it would
>> be better to follow GetPSRFromPSTATE pseudocode.
>
> Yes, I think that's the best thing to do. We've been skating
> by on CPSR and SPSR being the same thing and it's just
> stopped working.
Would you like me to work on this, or is it something the arm
maintainers would fix?
--
Rebecca Cran
next prev parent reply other threads:[~2020-12-14 18:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-11 5:13 [PATCH 0/2] target/arm: Add support for DIT (Data Independent Timing) Rebecca Cran
2020-12-11 5:13 ` [PATCH 1/2] target/arm: add support for FEAT_DIT, Data Independent Timing Rebecca Cran
2020-12-11 14:08 ` Richard Henderson
2020-12-11 19:33 ` Rebecca Cran
2020-12-11 19:51 ` Richard Henderson
2020-12-11 21:37 ` Peter Maydell
2020-12-14 18:11 ` Rebecca Cran [this message]
2020-12-14 18:48 ` Peter Maydell
2020-12-11 5:13 ` [PATCH 2/2] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU Rebecca Cran
2020-12-11 14:09 ` Richard Henderson
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