From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55421) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZKXuf-0005FE-RC for qemu-devel@nongnu.org; Wed, 29 Jul 2015 16:25:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZKXua-0002zy-UZ for qemu-devel@nongnu.org; Wed, 29 Jul 2015 16:25:17 -0400 Received: from mail-bn1bbn0100.outbound.protection.outlook.com ([157.56.111.100]:28640 helo=na01-bn1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZKXua-0002zs-QP for qemu-devel@nongnu.org; Wed, 29 Jul 2015 16:25:12 -0400 From: Alistair Francis Date: Wed, 29 Jul 2015 13:25:08 -0700 Message-ID: <8b7bbc961a86e73de14391616fae43f79373f38d.1438200827.git.alistair.francis@xilinx.com> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v1 14/15] misc: Introduce ZynqMP IOU SLCR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, edgar.iglesias@gmail.com, afaerber@suse.de From: Peter Crosthwaite IOU = I/O Unit SLCR = System Level Control Registers This IP is a misc collections of control registers that switch various properties of system IPs. Currently the only thing implemented is the SD_SLOTTYPE control (implemented as a GPIO output). Signed-off-by: Peter Crosthwaite --- hw/misc/Makefile.objs | 1 + hw/misc/xlnx-zynqmp-iou-slcr.c | 113 ++++++++++++++++++++++++++++++++ include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 +++++++++++++ 3 files changed, 161 insertions(+), 0 deletions(-) create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 4aa76ff..8aa6038 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -36,6 +36,7 @@ obj-$(CONFIG_OMAP) += omap_sdrc.o obj-$(CONFIG_OMAP) += omap_tap.o obj-$(CONFIG_SLAVIO) += slavio_misc.o obj-$(CONFIG_ZYNQ) += zynq_slcr.o +obj-$(CONFIG_ZYNQ) += xlnx-zynqmp-iou-slcr.o obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o obj-$(CONFIG_PVPANIC) += pvpanic.o diff --git a/hw/misc/xlnx-zynqmp-iou-slcr.c b/hw/misc/xlnx-zynqmp-iou-slcr.c new file mode 100644 index 0000000..35b989c --- /dev/null +++ b/hw/misc/xlnx-zynqmp-iou-slcr.c @@ -0,0 +1,113 @@ +/* + * Xilinx ZynqMP IOU System Level Control Registers (SLCR) + * + * Copyright (c) 2013 Xilinx Inc + * Copyright (c) 2013 Peter Crosthwaite + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hw/misc/xlnx-zynqmp-iou-slcr.h" + +#ifndef XLNX_ZYNQMP_IOU_SLCR_ERR_DEBUG +#define XLNX_ZYNQMP_IOU_SLCR_ERR_DEBUG 0 +#endif + +REG32(SD_SLOTTYPE, 0x310) + #define R_SD_SLOTTYPE_RSVD 0xffff7ffe + +static const RegisterAccessInfo xlnx_zynqmp_iou_slcr_regs_info[] = { + { .name = "SD Slot TYPE", .decode.addr = A_SD_SLOTTYPE, + .rsvd = R_SD_SLOTTYPE_RSVD, + .gpios = (RegisterGPIOMapping []) { + { .name = "SD0_SLOTTYPE", .bit_pos = 0 }, + { .name = "SD1_SLOTTYPE", .bit_pos = 15 }, + {}, + } + } + /* FIXME: Complete device model */ +}; + +static void xlnx_zynqmp_iou_slcr_reset(DeviceState *dev) +{ + XlnxZynqMPIOUSLCR *s = XLNX_ZYNQMP_IOU_SLCR(dev); + int i; + + for (i = 0; i < XLNX_ZYNQ_MP_IOU_SLCR_R_MAX; ++i) { + register_reset(&s->regs_info[i]); + } +} + +static const MemoryRegionOps xlnx_zynqmp_iou_slcr_ops = { + .read = register_read_memory_le, + .write = register_write_memory_le, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + } +}; + +static void xlnx_zynqmp_iou_slcr_init(Object *obj) +{ + XlnxZynqMPIOUSLCR *s = XLNX_ZYNQMP_IOU_SLCR(obj); + + memory_region_init(&s->iomem, obj, "MMIO", XLNX_ZYNQ_MP_IOU_SLCR_R_MAX * 4); + register_init_block32(DEVICE(obj), xlnx_zynqmp_iou_slcr_regs_info, + ARRAY_SIZE(xlnx_zynqmp_iou_slcr_regs_info), + s->regs_info, s->regs, &s->iomem, + &xlnx_zynqmp_iou_slcr_ops, + XLNX_ZYNQMP_IOU_SLCR_ERR_DEBUG); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static const VMStateDescription vmstate_xlnx_zynqmp_iou_slcr = { + .name = "xlnx_zynqmp_iou_slcr", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIOUSLCR, + XLNX_ZYNQ_MP_IOU_SLCR_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void xlnx_zynqmp_iou_slcr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = xlnx_zynqmp_iou_slcr_reset; + dc->vmsd = &vmstate_xlnx_zynqmp_iou_slcr; +} + +static const TypeInfo xlnx_zynqmp_iou_slcr_info = { + .name = TYPE_XLNX_ZYNQMP_IOU_SLCR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxZynqMPIOUSLCR), + .class_init = xlnx_zynqmp_iou_slcr_class_init, + .instance_init = xlnx_zynqmp_iou_slcr_init, +}; + +static void xlnx_zynqmp_iou_slcr_register_types(void) +{ + type_register_static(&xlnx_zynqmp_iou_slcr_info); +} + +type_init(xlnx_zynqmp_iou_slcr_register_types) diff --git a/include/hw/misc/xlnx-zynqmp-iou-slcr.h b/include/hw/misc/xlnx-zynqmp-iou-slcr.h new file mode 100644 index 0000000..1a3f7e9 --- /dev/null +++ b/include/hw/misc/xlnx-zynqmp-iou-slcr.h @@ -0,0 +1,47 @@ +/* + * Xilinx ZynqMP IOU system level control registers (SLCR) + * + * Copyright (c) 2013 Xilinx Inc + * Copyright (c) 2013 Peter Crosthwaite + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hw/sysbus.h" +#include "hw/register.h" + +#define TYPE_XLNX_ZYNQMP_IOU_SLCR "xlnx_zynqmp-iou-slcr" + +#define XLNX_ZYNQMP_IOU_SLCR(obj) \ + OBJECT_CHECK(XlnxZynqMPIOUSLCR, (obj), TYPE_XLNX_ZYNQMP_IOU_SLCR) + +#define XLNX_ZYNQ_MP_IOU_SLCR_R_MAX (0x314/4) + +typedef struct XlnxZynqMPIOUSLCR XlnxZynqMPIOUSLCR; + +struct XlnxZynqMPIOUSLCR { + /*< private >*/ + SysBusDevice busdev; + + /*< public >*/ + MemoryRegion iomem; + + uint32_t regs[XLNX_ZYNQ_MP_IOU_SLCR_R_MAX]; + RegisterInfo regs_info[XLNX_ZYNQ_MP_IOU_SLCR_R_MAX]; +}; -- 1.7.1