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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id x14sm2480328pjl.27.2021.12.03.05.00.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Dec 2021 05:00:12 -0800 (PST) Subject: Re: [PATCH v2 2/3] target/ppc: Implement Vector Extract Mask To: matheus.ferst@eldorado.org.br, qemu-devel@nongnu.org, qemu-ppc@nongnu.org References: <20211112141430.631732-1-matheus.ferst@eldorado.org.br> <20211112141430.631732-3-matheus.ferst@eldorado.org.br> From: Richard Henderson Message-ID: <8b929a58-efaa-08af-2183-de4fe1a8389d@linaro.org> Date: Fri, 3 Dec 2021 05:00:10 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211112141430.631732-3-matheus.ferst@eldorado.org.br> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.938, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: groug@kaod.org, danielhb413@gmail.com, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/12/21 6:14 AM, matheus.ferst@eldorado.org.br wrote: > From: Matheus Ferst > > Implement the following PowerISA v3.1 instructions: > vextractbm: Vector Extract Byte Mask > vextracthm: Vector Extract Halfword Mask > vextractwm: Vector Extract Word Mask > vextractdm: Vector Extract Doubleword Mask > vextractqm: Vector Extract Quadword Mask > > Suggested-by: Richard Henderson > Signed-off-by: Matheus Ferst > --- > v2: > - Applied rth suggestion to do_vextractm > --- > target/ppc/insn32.decode | 6 +++ > target/ppc/translate/vmx-impl.c.inc | 60 +++++++++++++++++++++++++++++ > 2 files changed, 66 insertions(+) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index 9a28f1d266..639ac22bf0 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -419,6 +419,12 @@ VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb > VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb > VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb > > +VEXTRACTBM 000100 ..... 01000 ..... 11001000010 @VX_tb > +VEXTRACTHM 000100 ..... 01001 ..... 11001000010 @VX_tb > +VEXTRACTWM 000100 ..... 01010 ..... 11001000010 @VX_tb > +VEXTRACTDM 000100 ..... 01011 ..... 11001000010 @VX_tb > +VEXTRACTQM 000100 ..... 01100 ..... 11001000010 @VX_tb > + > # VSX Load/Store Instructions > > LXV 111101 ..... ..... ............ . 001 @DQ_TSX > diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc > index 58aca58f0f..dd7337c2f2 100644 > --- a/target/ppc/translate/vmx-impl.c.inc > +++ b/target/ppc/translate/vmx-impl.c.inc > @@ -1539,6 +1539,66 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a) > return true; > } > > +static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece) > +{ > + const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece; > + TCGv_i64 t, b, tmp; > + > + REQUIRE_INSNS_FLAGS2(ctx, ISA310); > + REQUIRE_VECTOR(ctx); > + > + t = tcg_const_i64(0); > + b = tcg_temp_new_i64(); > + tmp = tcg_temp_new_i64(); > + > + for (int w = 0; w < 2; w++) { > + get_avr64(b, a->vrb, w); > + > + for (int i = 0; i < elem_count_half; i++) { > + int in_bit = (i + 1) * elem_width - 1; > + int out_bit = w * elem_count_half + i; > + > + if (in_bit > out_bit) { > + tcg_gen_shri_i64(tmp, b, in_bit - out_bit); > + } else { > + tcg_gen_shli_i64(tmp, b, out_bit - in_bit); > + } > + tcg_gen_andi_i64(tmp, tmp, 1 << out_bit); > + tcg_gen_or_i64(t, t, tmp); > + } > + } > + tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], t); Pardon me. I realized after the fact that we can run the same algorithm as for mtvsrm (in the next patch) in reverse. & dup(1) .......a.......b.......c.......d.......e.......f.......g.......h >> 32 - 4 ...................................a.......b.......c.......d.... | .......a.......b.......c.......d...a...e...b...f...c...g...d...h >> 16 - 2 .....................a.......b.......c.......d...a...e...b...f.. | .......a.......b.....a.c.....b.d...a.c.e...b.d.f.a.c.e.g.b.d.f.h >> 8 - 1 ..............a.......b.....a.c.....b.d...a.c.e...b.d.f.a.c.e.g. | .......a......ab.....abc....abcd...abcde..abcdef.abcdefgabcdefgh & 0xff ........................................................abcdefgh where one of the two final masks can be done via deposit: tcg_gen_andi_i64(hi, hi, 0xff); tcg_gen_deposit_i64(lo, lo, hi, 8, 56); Which will reduce the instruction count of this implementation by half. r~