[PATCH v3] drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish

[PATCH v3] drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish

[Lang Yu]

Some clients(e.g., kfd) query sclk/mclk through this function.
Because cyan skillfish doesn't support dpm. For sclk, set min/max
to CYAN_SKILLFISH_SCLK_MIN/CYAN_SKILLFISH_SCLK_MAX(to maintain the
existing logic).For others, set both min and max to current value.

Before this patch:
 # /opt/rocm/opencl/bin/clinfo

 Max clock frequency:                           0Mhz

After this patch:
 # /opt/rocm/opencl/bin/clinfo

 Max clock frequency:                           2000Mhz

v2:
 - Maintain the existing min/max sclk logic.(Lijo)
v3:
 - Avoid fetching metrics table twice.(Lijo)

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
 .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c   | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 2238ee19c222..dfc5d6801f9f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -552,6 +552,36 @@ static int cyan_skillfish_od_edit_dpm_table(struct smu_context *smu,
 	return ret;
 }
 
+static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu,
+						enum smu_clk_type clk_type,
+						uint32_t *min,
+						uint32_t *max)
+{
+	int ret = 0;
+	uint32_t low, high;
+
+	switch (clk_type) {
+	case SMU_GFXCLK:
+	case SMU_SCLK:
+		low = CYAN_SKILLFISH_SCLK_MIN;
+		high = CYAN_SKILLFISH_SCLK_MAX;
+		break;
+	default:
+		ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low);
+		if (ret)
+			return ret;
+		high = low;
+		break;
+	}
+
+	if (min)
+		*min = low;
+	if (max)
+		*max = high;
+
+	return 0;
+}
+
 static const struct pptable_funcs cyan_skillfish_ppt_funcs = {
 
 	.check_fw_status = smu_v11_0_check_fw_status,
@@ -565,6 +595,7 @@ static const struct pptable_funcs cyan_skillfish_ppt_funcs = {
 	.is_dpm_running = cyan_skillfish_is_dpm_running,
 	.get_gpu_metrics = cyan_skillfish_get_gpu_metrics,
 	.od_edit_dpm_table = cyan_skillfish_od_edit_dpm_table,
+	.get_dpm_ultimate_freq = cyan_skillfish_get_dpm_ultimate_freq,
 	.register_irq_handler = smu_v11_0_register_irq_handler,
 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
 	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
-- 
2.25.1

Re: [PATCH v3] drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish

[Lazar, Lijo]

On 1/24/2022 7:46 PM, Lang Yu wrote:
> Some clients(e.g., kfd) query sclk/mclk through this function.
> Because cyan skillfish doesn't support dpm. For sclk, set min/max
> to CYAN_SKILLFISH_SCLK_MIN/CYAN_SKILLFISH_SCLK_MAX(to maintain the
> existing logic).For others, set both min and max to current value.
> 
> Before this patch:
>   # /opt/rocm/opencl/bin/clinfo
> 
>   Max clock frequency:                           0Mhz
> 
> After this patch:
>   # /opt/rocm/opencl/bin/clinfo
> 
>   Max clock frequency:                           2000Mhz
> 
> v2:
>   - Maintain the existing min/max sclk logic.(Lijo)
> v3:
>   - Avoid fetching metrics table twice.(Lijo)
> 
> Signed-off-by: Lang Yu <Lang.Yu@amd.com>

Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>

Thanks,
Lijo

> ---
>   .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c   | 31 +++++++++++++++++++
>   1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> index 2238ee19c222..dfc5d6801f9f 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> @@ -552,6 +552,36 @@ static int cyan_skillfish_od_edit_dpm_table(struct smu_context *smu,
>   	return ret;
>   }
>   
> +static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu,
> +						enum smu_clk_type clk_type,
> +						uint32_t *min,
> +						uint32_t *max)
> +{
> +	int ret = 0;
> +	uint32_t low, high;
> +
> +	switch (clk_type) {
> +	case SMU_GFXCLK:
> +	case SMU_SCLK:
> +		low = CYAN_SKILLFISH_SCLK_MIN;
> +		high = CYAN_SKILLFISH_SCLK_MAX;
> +		break;
> +	default:
> +		ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low);
> +		if (ret)
> +			return ret;
> +		high = low;
> +		break;
> +	}
> +
> +	if (min)
> +		*min = low;
> +	if (max)
> +		*max = high;
> +
> +	return 0;
> +}
> +
>   static const struct pptable_funcs cyan_skillfish_ppt_funcs = {
>   
>   	.check_fw_status = smu_v11_0_check_fw_status,
> @@ -565,6 +595,7 @@ static const struct pptable_funcs cyan_skillfish_ppt_funcs = {
>   	.is_dpm_running = cyan_skillfish_is_dpm_running,
>   	.get_gpu_metrics = cyan_skillfish_get_gpu_metrics,
>   	.od_edit_dpm_table = cyan_skillfish_od_edit_dpm_table,
> +	.get_dpm_ultimate_freq = cyan_skillfish_get_dpm_ultimate_freq,
>   	.register_irq_handler = smu_v11_0_register_irq_handler,
>   	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
>   	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
>