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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [PATCH 2/2] [RFC] clk: stm32mp1: Handle SoC speed grade configs
Date: Sun, 14 Jun 2020 17:23:38 +0200	[thread overview]
Message-ID: <8bc89d1a-fe4d-6188-8dec-054fa71fd0be@denx.de> (raw)
In-Reply-To: <85d6188d564244249824619d11d7a718@SFHDAG6NODE3.st.com>

On 5/13/20 11:12 AM, Patrick DELAUNAY wrote:
> Dear Marek,

Hi,

[...]

>> @@ -1783,6 +1800,11 @@ static int stm32mp1_clktree(struct udevice *dev)
>>  			continue;
>>
>>  		fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
>> +		if (!fracv) {
>> +			fracv = ofnode_read_u32_default(plloff[i],
>> +					stm32mp1_is_df() ? "frac-df" : "frac-ac",
>> +					0);
>> +		}
>>  		pll_config(priv, i, pllcfg[i], fracv);
>>  		ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
>>  		if (!ret) {
>> --
>> 2.25.1
> 
> The 2 speed grade will be supported with OPP information and HW support,present in kernel device tree (upstream in progress) 

Great, thanks!

  parent reply	other threads:[~2020-06-14 15:23 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-12 17:07 [PATCH 1/2] [RFC] ARM: stm32: Make bsec available in SPL Marek Vasut
2020-05-12 17:07 ` [PATCH 2/2] [RFC] clk: stm32mp1: Handle SoC speed grade configs Marek Vasut
2020-05-13  9:12   ` Patrick DELAUNAY
2020-05-13 10:52     ` Marek Vasut
2020-05-13 12:23       ` Patrick DELAUNAY
2020-05-13 12:38         ` Marek Vasut
2020-06-14 15:23     ` Marek Vasut [this message]
2020-05-13  9:05 ` [PATCH 1/2] [RFC] ARM: stm32: Make bsec available in SPL Patrick DELAUNAY

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