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([2001:df0:0:200c:c850:272b:f208:39af]) by smtp.gmail.com with ESMTPSA id w2sm12311031pgm.18.2019.11.10.11.26.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 10 Nov 2019 11:26:38 -0800 (PST) Subject: Re: [PATCH] zorro_esp: increase maximum dma length to 65536 bytes To: Kars de Jong Cc: James Bottomley , "Martin K. Petersen" , linux-scsi@vger.kernel.org, linux-m68k@vger.kernel.org References: <20191109191400.8999-1-jongk@linux-m68k.org> <1573330351.3650.4.camel@linux.ibm.com> <6b914b12-cbc7-6fe6-7cba-3e89b2f6f19b@gmail.com> From: Michael Schmitz Message-ID: <8c356175-e490-68c0-6114-5192eedc3a4f@gmail.com> Date: Mon, 11 Nov 2019 08:26:32 +1300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-m68k-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-m68k@vger.kernel.org Hi Kars, thanks for your patch! On 10/11/19 10:01 PM, Kars de Jong wrote: > Hi Michael, > > Op zo 10 nov. 2019 om 03:36 schreef Michael Schmitz : >> All of the old board-specific drivers used a max transfer length of >> 0x1000000, only the fastlane driver used 0xfffc. > Yes, I also found this when checking the old drivers. > >> That lower limit might >> be due to a DMA limitation on the fastlane board. We could accommodate >> the different limit for this board by using a board-specific >> dma_length_limit() callback... > Yes, I think that's the best idea for now. Oktagon also used to have a > different limit but that was never ported to the new ESP core. I can't remember the details, but as far as I recall it, the Oktagon used pseudo-DMA rather than hardware DMA. At the time I started porting Zorro ESP drivers to the new core, pseudo-DMA code was available for Mac only, and no PIO transfer for data phases at all, so I decided to leave that out altogether. Might be a lot easier now that Finn has moved the PIO support code into the core driver. Someone could start with a PIO mode driver and add PDMA later. >>> case for any of the cards the zorro_esp drives, it might be better to >>> lower the max length to 61440 (64k-4k) so the residual is a page. >> For the benefit of keeping the code simple, and avoid retesting the >> fastlane board, that might indeed be the better solution. > But it's slower... :-P I wonder what max. transfer size had been used so far, in the majority of cases. I hadn't observed this bug in my tests of the ESP driver on elgar. So it might not matter so much in practice. > Also, I may be adding another board-specific version for the Blizzard > 12x0 IV to enable 24-bit transfers, like the am53c974 driver does, in > a later patch. If we can differentiate between the Mark IV board and the Mark II board in a reliable way, fine. I can't remember whether I've had a report on that ever. I'd suggest to change the transfer size limit to 60k in the first instance, and add board-specific tweaks as needed when you add 24 bit DMA support for the Mark IV. Cheers,     Michael > > Kind regards, > > Kars.