From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0231AC43142 for ; Thu, 2 Aug 2018 07:24:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A0EE3208DD for ; Thu, 2 Aug 2018 07:24:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A0EE3208DD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727369AbeHBJOV (ORCPT ); Thu, 2 Aug 2018 05:14:21 -0400 Received: from mx2.suse.de ([195.135.220.15]:49000 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726631AbeHBJOV (ORCPT ); Thu, 2 Aug 2018 05:14:21 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id CFE31ADBF; Thu, 2 Aug 2018 07:24:28 +0000 (UTC) Subject: Re: [PATCH 8/9] dt-bindings: interrupt-controller: RISC-V PLIC documentation To: Christoph Hellwig , tglx@linutronix.de, palmer@sifive.com, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: anup@brainfault.org, atish.patra@wdc.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, shorne@gmail.com, Palmer Dabbelt References: <20180726143723.16585-1-hch@lst.de> <20180726143723.16585-9-hch@lst.de> From: Nikolay Borisov Openpgp: preference=signencrypt Autocrypt: addr=nborisov@suse.com; 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Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180726143723.16585-9-hch@lst.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 26.07.2018 17:37, Christoph Hellwig wrote: > From: Palmer Dabbelt > > This patch adds documentation for the platform-level interrupt > controller (PLIC) found in all RISC-V systems. This interrupt > controller routes interrupts from all the devices in the system to each > hart-local interrupt controller. > > Note: the DTS bindings for the PLIC aren't set in stone yet, as we might > want to change how we're specifying holes in the hart list. > > Signed-off-by: Palmer Dabbelt > --- > .../interrupt-controller/riscv,plic0.txt | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt > new file mode 100644 > index 000000000000..99cd359dbd43 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt > @@ -0,0 +1,55 @@ > +RISC-V Platform-Level Interrupt Controller (PLIC) > +------------------------------------------------- > + > +The RISC-V supervisor ISA specification allows for the presence of a > +platform-level interrupt controller (PLIC). The PLIC connects all external > +interrupts in the system to all hart contexts in the system, via the external > +interrupt source in each hart's hart-local interrupt controller (HLIC). A hart > +context is a privilege mode in a hardware execution thread. For example, in > +an 4 core system with 2-way SMT, you have 8 harts and probably at least two > +privilege modes per hart; machine mode and supervisor mode. > + > +Each interrupt can be enabled on per-context basis. Any context can claim > +a pending enabled interrupt and then release it once it has been handled. > + > +Each interrupt has a configurable priority. Higher priority interrupts are > +serviced firs. Each context can specify a priority threshold. Interrupts ^^ missing 't' > +with priority below this threshold will not cause the PLIC to raise its > +interrupt line leading to the context. > + > +While the PLIC supports both edge-triggered and level-triggered interrupts, > +interrupt handlers are oblivious to this distinction and therefor it is not ^^ missing 'e' > +specific in the PLIC device-tree binding. > + > +While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > +"riscv,plic0" device is a concrete implementation of the PLIC that contains a > +specific memory layout. More details about the memory layout of the > +"riscv,plic0" device can be found as a comment in the device driver, or as part > +of the SiFive U5 Coreplex Series Manual (page 22 of the PDF of version 1.0) > + > + > +Required properties: > +- compatible : "riscv,plic0" > +- #address-cells : should be <0> > +- #interrupt-cells : should be <1> > +- interrupt-controller : Identifies the node as an interrupt controller > +- reg : Should contain 1 register range (address and length) > +- interrupts-extended : Specifies which contexts are connected to the PLIC, > + with "-1" specifying that a context is not present. > + > +Example: > + > + plic: interrupt-controller@c000000 { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + compatible = "riscv,plic0"; > + interrupt-controller; > + interrupts-extended = < > + &cpu0-intc 11 > + &cpu1-intc 11 &cpu1-intc 9 > + &cpu2-intc 11 &cpu2-intc 9 > + &cpu3-intc 11 &cpu3-intc 9 > + &cpu4-intc 11 &cpu4-intc 9>; > + reg = <0xc000000 0x4000000>; > + riscv,ndev = <10>; > + }; > From mboxrd@z Thu Jan 1 00:00:00 1970 From: nborisov@suse.com (Nikolay Borisov) Date: Thu, 2 Aug 2018 10:24:26 +0300 Subject: [PATCH 8/9] dt-bindings: interrupt-controller: RISC-V PLIC documentation In-Reply-To: <20180726143723.16585-9-hch@lst.de> References: <20180726143723.16585-1-hch@lst.de> <20180726143723.16585-9-hch@lst.de> Message-ID: <8cbdbd76-c152-f7d6-9f65-96b433a3f4ae@suse.com> To: linux-riscv@lists.infradead.org List-Id: linux-riscv.lists.infradead.org On 26.07.2018 17:37, Christoph Hellwig wrote: > From: Palmer Dabbelt > > This patch adds documentation for the platform-level interrupt > controller (PLIC) found in all RISC-V systems. This interrupt > controller routes interrupts from all the devices in the system to each > hart-local interrupt controller. > > Note: the DTS bindings for the PLIC aren't set in stone yet, as we might > want to change how we're specifying holes in the hart list. > > Signed-off-by: Palmer Dabbelt > --- > .../interrupt-controller/riscv,plic0.txt | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt > new file mode 100644 > index 000000000000..99cd359dbd43 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt > @@ -0,0 +1,55 @@ > +RISC-V Platform-Level Interrupt Controller (PLIC) > +------------------------------------------------- > + > +The RISC-V supervisor ISA specification allows for the presence of a > +platform-level interrupt controller (PLIC). The PLIC connects all external > +interrupts in the system to all hart contexts in the system, via the external > +interrupt source in each hart's hart-local interrupt controller (HLIC). A hart > +context is a privilege mode in a hardware execution thread. For example, in > +an 4 core system with 2-way SMT, you have 8 harts and probably at least two > +privilege modes per hart; machine mode and supervisor mode. > + > +Each interrupt can be enabled on per-context basis. Any context can claim > +a pending enabled interrupt and then release it once it has been handled. > + > +Each interrupt has a configurable priority. Higher priority interrupts are > +serviced firs. Each context can specify a priority threshold. Interrupts ^^ missing 't' > +with priority below this threshold will not cause the PLIC to raise its > +interrupt line leading to the context. > + > +While the PLIC supports both edge-triggered and level-triggered interrupts, > +interrupt handlers are oblivious to this distinction and therefor it is not ^^ missing 'e' > +specific in the PLIC device-tree binding. > + > +While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > +"riscv,plic0" device is a concrete implementation of the PLIC that contains a > +specific memory layout. More details about the memory layout of the > +"riscv,plic0" device can be found as a comment in the device driver, or as part > +of the SiFive U5 Coreplex Series Manual (page 22 of the PDF of version 1.0) > + > + > +Required properties: > +- compatible : "riscv,plic0" > +- #address-cells : should be <0> > +- #interrupt-cells : should be <1> > +- interrupt-controller : Identifies the node as an interrupt controller > +- reg : Should contain 1 register range (address and length) > +- interrupts-extended : Specifies which contexts are connected to the PLIC, > + with "-1" specifying that a context is not present. > + > +Example: > + > + plic: interrupt-controller at c000000 { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + compatible = "riscv,plic0"; > + interrupt-controller; > + interrupts-extended = < > + &cpu0-intc 11 > + &cpu1-intc 11 &cpu1-intc 9 > + &cpu2-intc 11 &cpu2-intc 9 > + &cpu3-intc 11 &cpu3-intc 9 > + &cpu4-intc 11 &cpu4-intc 9>; > + reg = <0xc000000 0x4000000>; > + riscv,ndev = <10>; > + }; >