From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Gonzalez Subject: [PATCH v4] PCI: qcom: Use default config space read function Date: Mon, 18 Mar 2019 18:14:45 +0100 Message-ID: <8cd24928-54d0-c320-b53f-08332d434477@free.fr> References: <94bb3f22-c5a7-1891-9d89-42a520e9a592@free.fr> <65321fe3-ca29-c454-63ae-98a46c2e5158@mm-sol.com> <1205cbfb-ac06-63a5-9401-75d4e68b15b5@free.fr> <38ad143b-3b07-4d19-8ccd-ca39fb51e53d@free.fr> <7d3d788a-d6a3-a70b-adab-6c65771cacc4@free.fr> <3c76613e-e60d-94b8-dd6f-b8f4e1928263@linaro.org> <2f901228-52db-7661-8257-ca8fd2ff2a46@free.fr> <29664b43-535c-c4b1-a93d-18f49687f929@linaro.org> <9c5a7620-e9ed-82d6-0708-34fe33e39030@linaro.org> <29d33e81-fe8d-7fd9-843d-cc53ea6c9586@free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Stanimir Varbanov , Srinivas Kandagatla , Bjorn Helgaas Cc: Andy Gross , David Brown , Bjorn Andersson , PCI , MSM , LKML , Jeffrey Hugo List-Id: linux-arm-msm@vger.kernel.org We don't need to fudge the device class in qcom_pcie_rd_own_conf() because dw_pcie_setup_rc() already does the right thing: /* Program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); However, the above has no effect on 8064, thus a fixup is required. Signed-off-by: Marc Gonzalez Tested-by: Srinivas Kandagatla --- Changes from v3 to v4: Define and use DEV_ID_8064 (not in include/linux/pci_ids.h because not shared) --- drivers/pci/controller/dwc/pcie-qcom.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index d185ea5fe996..712a83354f9d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1129,25 +1129,8 @@ static int qcom_pcie_host_init(struct pcie_port *pp) return ret; } -static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, - u32 *val) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - - /* the device class is not reported correctly from the register */ - if (where == PCI_CLASS_REVISION && size == 4) { - *val = readl(pci->dbi_base + PCI_CLASS_REVISION); - *val &= 0xff; /* keep revision id */ - *val |= PCI_CLASS_BRIDGE_PCI << 16; - return PCIBIOS_SUCCESSFUL; - } - - return dw_pcie_read(pci->dbi_base + where, size, val); -} - static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { .host_init = qcom_pcie_host_init, - .rd_own_conf = qcom_pcie_rd_own_conf, }; /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ @@ -1309,6 +1292,14 @@ static const struct of_device_id qcom_pcie_match[] = { { } }; +#define DEV_ID_8064 0x0101 + +static void qcom_fixup_class(struct pci_dev *dev) +{ + dev->class = PCI_CLASS_BRIDGE_PCI << 8; +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, DEV_ID_8064, qcom_fixup_class); + static struct platform_driver qcom_pcie_driver = { .probe = qcom_pcie_probe, .driver = { -- 2.17.1