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Thu, 4 Feb 2021 07:23:46 +0000 (GMT) Received: from [9.199.62.53] (unknown [9.199.62.53]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Feb 2021 07:23:46 +0000 (GMT) Subject: Re: [PATCH v3 1/2] powerpc: sstep: Fix load-store and update emulation From: Sandipan Das To: mpe@ellerman.id.au References: <20210204071432.116439-1-sandipan@linux.ibm.com> Message-ID: <8d1021ea-0082-b3fb-1b71-ff6986a1ceb7@linux.ibm.com> Date: Thu, 4 Feb 2021 12:53:45 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: <20210204071432.116439-1-sandipan@linux.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.737 definitions=2021-02-04_03:2021-02-04, 2021-02-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 mlxscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2102040041 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ravi.bangoria@linux.ibm.com, ananth@linux.ibm.com, jniethe5@gmail.com, paulus@samba.org, naveen.n.rao@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, dja@axtens.net Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 04/02/21 12:44 pm, Sandipan Das wrote: > The Power ISA says that the fixed-point load and update > instructions must neither use R0 for the base address (RA) > nor have the destination (RT) and the base address (RA) as > the same register. Similarly, for fixed-point stores and > floating-point loads and stores, the instruction is invalid > when R0 is used as the base address (RA). > > This is applicable to the following instructions. > * Load Byte and Zero with Update (lbzu) > * Load Byte and Zero with Update Indexed (lbzux) > * Load Halfword and Zero with Update (lhzu) > * Load Halfword and Zero with Update Indexed (lhzux) > * Load Halfword Algebraic with Update (lhau) > * Load Halfword Algebraic with Update Indexed (lhaux) > * Load Word and Zero with Update (lwzu) > * Load Word and Zero with Update Indexed (lwzux) > * Load Word Algebraic with Update Indexed (lwaux) > * Load Doubleword with Update (ldu) > * Load Doubleword with Update Indexed (ldux) > * Load Floating Single with Update (lfsu) > * Load Floating Single with Update Indexed (lfsux) > * Load Floating Double with Update (lfdu) > * Load Floating Double with Update Indexed (lfdux) > * Store Byte with Update (stbu) > * Store Byte with Update Indexed (stbux) > * Store Halfword with Update (sthu) > * Store Halfword with Update Indexed (sthux) > * Store Word with Update (stwu) > * Store Word with Update Indexed (stwux) > * Store Doubleword with Update (stdu) > * Store Doubleword with Update Indexed (stdux) > * Store Floating Single with Update (stfsu) > * Store Floating Single with Update Indexed (stfsux) > * Store Floating Double with Update (stfdu) > * Store Floating Double with Update Indexed (stfdux) > > E.g. the following behaviour is observed for an invalid > load and update instruction having RA = RT. > > While an userspace program having an instruction word like > 0xe9ce0001, i.e. ldu r14, 0(r14), runs without getting > receiving a SIGILL on a Power system (observed on P8 and > P9), the outcome of executing that instruction word varies > and its behaviour can be considered to be undefined. > > Attaching an uprobe at that instruction's address results > in emulation which currently performs the load as well as > writes the effective address back to the base register. > This might not match the outcome from hardware. > > To remove any inconsistencies, this adds additional checks > for the aforementioned instructions to make sure that the > emulation infrastructure treats them as unknown. The kernel > can then fallback to executing such instructions on hardware. > > Fixes: 0016a4cf5582 ("powerpc: Emulate most Book I instructions in emulate_step()") > Signed-off-by: Sandipan Das > --- > Previous versions can be found at: > v2: https://lore.kernel.org/linuxppc-dev/20210203063841.431063-1-sandipan@linux.ibm.com/ > v1: https://lore.kernel.org/linuxppc-dev/20201119054139.244083-1-sandipan@linux.ibm.com/ > > Changes in v3: > - Dropped CONFIG_PPC_FPU check as suggested by Michael. > - Consolidated the checks as suggested by Naveen. Sorry. Missed these in the changelog: - Consolidated load/store changes into a single patch. - Included floating-point load/store and update instructions. - Sandipan