From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.1 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8A5AC433ED for ; Sat, 8 May 2021 20:26:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9E9766101D for ; Sat, 8 May 2021 20:26:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9E9766101D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 23F376E0E8; Sat, 8 May 2021 20:26:22 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id 516E96E0E3 for ; Sat, 8 May 2021 20:26:19 +0000 (UTC) Received: from [IPv6:::1] (p578adb1c.dip0.t-ipconnect.de [87.138.219.28]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 4DBC682CDB; Sat, 8 May 2021 22:26:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1620505577; bh=XeBbc1nFhGdrldhJqUmRF98LGGbGXJ4jNz52mxWB7NY=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=j8XnkvNfBFWXkvddE7VUrk+WhGNQMagXXClba5zUnQdAHkZ2pkGsfVT0JfEnxJ7k2 ef0/mg9KFj1B9pzWMnzGRVKQ5haoB+N5Fn1MIj+ExGymzZt1tFl1k25rz984RhpVwb CHppI+Luh8uJETsQdam4Ix62uGC8o3wupaAI+u271c/dP33ANehMxv1JRPYk31IpRP LhZbId2zY/YHl5Q9AkBEnBpxyZDOdeWJcgu+MU0xzicPUCwuI6hqC/nY4JNfpifQtj jf6z2PAOXvXDLcmPaTYM8vPMVsPmE+xB/iWLizbB+n91BiysUJ9ekKGEZXapYsj+jb 12LOj61971ZWw== Subject: Re: [PATCH V3 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver To: Dave Stevenson References: <20210505100218.108024-1-marex@denx.de> <20210505100218.108024-2-marex@denx.de> From: Marek Vasut Message-ID: <8d2fbc9b-fb3e-aac9-566a-033c4bb218d7@denx.de> Date: Sat, 8 May 2021 22:16:07 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Loic Poulain , ch@denx.de, Douglas Anderson , DRI Development , Stephen Boyd , Philippe Schenker , Jagan Teki , Valentin Raevsky , Sam Ravnborg , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 5/7/21 2:48 PM, Dave Stevenson wrote: [...] >> +static void sn65dsi83_enable(struct drm_bridge *bridge) >> +{ >> + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); >> + unsigned int pval; >> + u16 val; >> + int ret; >> + >> + /* Clear reset, disable PLL */ >> + regmap_write(ctx->regmap, REG_RC_RESET, 0x00); >> + regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); > > Sorry, a further thread of discussion coming from the investigations > I've been involved with. > > You've powered up in pre_enable, and are sending the I2C writes in enable. > >>>From the docs for drm_bridge_funcs->enable[1] > > * The bridge can assume that the display pipe (i.e. clocks and timing > * signals) feeding it is running when this callback is called. This > * callback must enable the display link feeding the next bridge in the > * chain if there is one. > > So video is running when enable is called, and the DSI data lanes may > be HS. (Someone correct me if that is an incorrect reading of the > text). > > The SN65DSI84 datasheet table 7-2 Initialization Sequence gives init > seq 8 as being "Change DSI data lanes to HS state and start DSI video > stream", AFTER all the I2C has been completed except reading back > registers and checking for errors. > With video running you don't fulfil the second part of init seq 2 "the > DSI data lanes MUST be driven to LP11 state" > > My investigations have been over delaying starting the DSI video > stream until after enable, but reading the descriptive text for enable > I believe the Pi is correct to be sending video at that point. > I guess there is some ambiguity as to whether the clock lane is going > to be in HS mode during pre_enable. On the Pi the PHY and clocks will > be enabled prior to pre_enable to allow for sending DSI commands > during pre_enable, but it may not be true on other platforms. You have to make sure the clock lane is running and in HS mode when configuring the DSI83, otherwise the internal DSI83 state machine won't be able to operate. [...]