From: Jan Beulich <jbeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Paul Durrant <Paul.Durrant@citrix.com>, Wei Liu <wl@xen.org>,
Roger Pau Monne <roger.pau@citrix.com>
Subject: [Xen-devel] [PATCH v3 1/8] x86emul: support WBNOINVD
Date: Tue, 3 Sep 2019 11:37:09 +0200 [thread overview]
Message-ID: <8d4c8f8e-c80d-5979-f965-a13db2d81ea6@suse.com> (raw)
In-Reply-To: <347e51f2-e80c-992c-6d0b-3b2bfdb75cce@suse.com>
Rev 037 of Intel's ISA extensions document does not state intercept
behavior for the insn (I've been unofficially told that the distinction
is going to be by exit qualification, as I would have assumed
considering that this way it's sufficiently transparent to unaware
software, as using WBINVD in place of WBNOINVD is always correct, just
less efficient). Similarly AMD's PM volume 2 version 3.31 only states
that both use the same VMEXIT, but not how to distinugish them (other
than by decoding the insn). Therefore in the HVM case for now it'll be
backed by the same ->wbinvd_intercept() handlers.
Use this occasion and also add the two missing table entries for
CLDEMOTE, which doesn't require any further changes to make work.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
---
v3: Drop A attribute from public header addition. Comment out
cpu_has_wbnoinvd part of conditional. Extend description.
v2: Re-base. Convert wbnoinvd() inline function.
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -208,6 +208,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
{"avx512-bitalg",0x00000007, 0, CPUID_REG_ECX, 12, 1},
{"avx512-vpopcntdq",0x00000007,0,CPUID_REG_ECX, 14, 1},
{"rdpid", 0x00000007, 0, CPUID_REG_ECX, 22, 1},
+ {"cldemote", 0x00000007, 0, CPUID_REG_ECX, 25, 1},
{"avx512-4vnniw",0x00000007, 0, CPUID_REG_EDX, 2, 1},
{"avx512-4fmaps",0x00000007, 0, CPUID_REG_EDX, 3, 1},
@@ -256,6 +257,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
{"invtsc", 0x80000007, NA, CPUID_REG_EDX, 8, 1},
+ {"wbnoinvd", 0x80000008, NA, CPUID_REG_EBX, 9, 1},
{"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1},
{"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8},
{"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4},
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -146,6 +146,8 @@ static const char *const str_e8b[32] =
{
[ 0] = "clzero",
+ /* [ 8] */ [ 9] = "wbnoinvd",
+
[12] = "ibpb",
};
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -2212,6 +2212,7 @@ static int hvmemul_cache_op(
/* fall through */
case x86emul_invd:
case x86emul_wbinvd:
+ case x86emul_wbnoinvd:
alternative_vcall(hvm_funcs.wbinvd_intercept);
break;
}
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -1120,7 +1120,7 @@ static int write_msr(unsigned int reg, u
static int cache_op(enum x86emul_cache_op op, enum x86_segment seg,
unsigned long offset, struct x86_emulate_ctxt *ctxt)
{
- ASSERT(op == x86emul_wbinvd);
+ ASSERT(op == x86emul_wbinvd || op == x86emul_wbnoinvd);
/* Ignore the instruction if unprivileged. */
if ( !cache_flush_permitted(current->domain) )
@@ -1129,6 +1129,8 @@ static int cache_op(enum x86emul_cache_o
* newer linux uses this in some start-of-day timing loops.
*/
;
+ else if ( op == x86emul_wbnoinvd /* && cpu_has_wbnoinvd */ )
+ wbnoinvd();
else
wbinvd();
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1869,6 +1869,7 @@ in_protmode(
#define vcpu_has_fma4() (ctxt->cpuid->extd.fma4)
#define vcpu_has_tbm() (ctxt->cpuid->extd.tbm)
#define vcpu_has_clzero() (ctxt->cpuid->extd.clzero)
+#define vcpu_has_wbnoinvd() (ctxt->cpuid->extd.wbnoinvd)
#define vcpu_has_bmi1() (ctxt->cpuid->feat.bmi1)
#define vcpu_has_hle() (ctxt->cpuid->feat.hle)
@@ -5931,10 +5932,13 @@ x86_emulate(
break;
case X86EMUL_OPC(0x0f, 0x08): /* invd */
- case X86EMUL_OPC(0x0f, 0x09): /* wbinvd */
+ case X86EMUL_OPC(0x0f, 0x09): /* wbinvd / wbnoinvd */
generate_exception_if(!mode_ring0(), EXC_GP, 0);
fail_if(!ops->cache_op);
- if ( (rc = ops->cache_op(b == 0x09 ? x86emul_wbinvd
+ if ( (rc = ops->cache_op(b == 0x09 ? !repe_prefix() ||
+ !vcpu_has_wbnoinvd()
+ ? x86emul_wbinvd
+ : x86emul_wbnoinvd
: x86emul_invd,
x86_seg_none, 0,
ctxt)) != X86EMUL_OKAY )
--- a/xen/arch/x86/x86_emulate/x86_emulate.h
+++ b/xen/arch/x86/x86_emulate/x86_emulate.h
@@ -182,6 +182,7 @@ enum x86emul_cache_op {
x86emul_clwb,
x86emul_invd,
x86emul_wbinvd,
+ x86emul_wbnoinvd,
};
struct x86_emulate_state;
--- a/xen/include/asm-x86/system.h
+++ b/xen/include/asm-x86/system.h
@@ -16,6 +16,11 @@ static inline void wbinvd(void)
asm volatile ( "wbinvd" ::: "memory" );
}
+static inline void wbnoinvd(void)
+{
+ asm volatile ( "repe; wbinvd" : : : "memory" );
+}
+
static inline void clflush(const void *p)
{
asm volatile ( "clflush %0" :: "m" (*(const char *)p) );
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -236,6 +236,7 @@ XEN_CPUFEATURE(AVX512_VNNI, 6*32+11) /
XEN_CPUFEATURE(AVX512_BITALG, 6*32+12) /*A Support for VPOPCNT[B,W] and VPSHUFBITQMB */
XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A POPCNT for vectors of DW/QW */
XEN_CPUFEATURE(RDPID, 6*32+22) /*A RDPID instruction */
+XEN_CPUFEATURE(CLDEMOTE, 6*32+25) /*A CLDEMOTE instruction */
/* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */
XEN_CPUFEATURE(ITSC, 7*32+ 8) /* Invariant TSC */
@@ -243,6 +244,7 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /
/* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */
XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */
+XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */
XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */
/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
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next prev parent reply other threads:[~2019-09-03 9:37 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 9:35 [Xen-devel] [PATCH v3 0/8] x86emul: further work Jan Beulich
2019-09-03 9:37 ` Jan Beulich [this message]
2019-09-03 10:17 ` [Xen-devel] [PATCH v3 1/8] x86emul: support WBNOINVD Andrew Cooper
2019-09-03 9:37 ` [Xen-devel] [PATCH v3 2/8] x86/HVM: ignore guest INVD uses Jan Beulich
2019-09-03 9:43 ` Paul Durrant
2019-09-03 10:18 ` Andrew Cooper
2019-09-03 12:22 ` Jan Beulich
2019-09-03 9:39 ` [Xen-devel] [PATCH v3 3/8] x86emul: generalize invlpg() hook Jan Beulich
2019-09-03 9:39 ` [Xen-devel] [PATCH v3 4/8] x86emul: support INVPCID Jan Beulich
2019-09-03 9:39 ` [Xen-devel] [PATCH v3 5/8] x86emul: support MOVDIR{I,64B} insns Jan Beulich
2019-09-03 10:28 ` [Xen-devel] [PATCH v3 5/8] x86emul: support MOVDIR{I, 64B} insns Andrew Cooper
2019-09-03 12:25 ` Jan Beulich
2019-09-04 10:19 ` Andrew Cooper
2019-09-04 11:52 ` Jan Beulich
2019-09-03 9:40 ` [Xen-devel] [PATCH v3 6/8] x86/HVM: scale MPERF values reported to guests (on AMD) Jan Beulich
2019-09-03 9:41 ` [Xen-devel] [PATCH v3 7/8] x86emul: support RDPRU Jan Beulich
2019-09-03 12:34 ` Andrew Cooper
2019-09-03 13:05 ` Jan Beulich
2019-09-04 9:26 ` Jan Beulich
2019-09-04 9:46 ` Andrew Cooper
2019-09-03 9:42 ` [Xen-devel] [PATCH v3 8/8] x86/HVM: don't needlessly intercept APERF/MPERF/TSC MSR reads Jan Beulich
2019-09-04 23:16 ` Boris Ostrovsky
2019-09-05 6:31 ` Jan Beulich
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