From mboxrd@z Thu Jan  1 00:00:00 1970
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 18 Jul 2018 10:00:12 +0200
Subject: [U-Boot] [RFC PATCH 0/4] arm: zynq: implement FPGA load from SPL
In-Reply-To: <20180718074141.16539-1-luaraneda@gmail.com>
References: <20180718074141.16539-1-luaraneda@gmail.com>
Message-ID: <8d595d25-d5d2-b434-6cb2-2522dd07cf43@xilinx.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On 18.7.2018 09:41, Luis Araneda wrote:
> This series implements FPGA bitstream loading from SPL.
> Programming the FPGA from the SPL is necessary on some boards,
> like the Zybo, because the FPGA fabric routes the I2C bus to an
> EEPROM for reading the Ethernet MAC address.
> 
> The bitstream is loaded from a FIT image into a dynamically-allocated
> memory before programming the FPGA.
> 
> Additionally, some fixes are applied to compile the zynqpl driver
> for SPL, and to properly detect an FPGA from the SPL.
> 
> I'm not sure if the fixes are correct or I'm missing something,
> hence the RFC.
> 
> Tested on a Digilent Zybo Z7-20 board
> 
> Luis Araneda (4):
>   spl: fit: display a message when an FPGA image is loaded
>   drivers: fpga: zynqpl: fix compilation with SPL
>   arm: zynq: spl: fix FPGA initialization
>   arm: zynq: spl: implement FPGA load from FIT
> 
>  arch/arm/mach-zynq/spl.c | 42 ++++++++++++++++++++++++++++++++++++++++
>  common/spl/spl_fit.c     |  1 +
>  drivers/fpga/zynqpl.c    |  4 ++--
>  3 files changed, 45 insertions(+), 2 deletions(-)
> 

Can you please also send defconfig/config changes?
Separate patch is fine.

Thanks,
Michal